This is an archive of the discontinued LLVM Phabricator instance.

Differential D67062

AMDGPU/GlobalISel: Make 16-bit constants legal
ClosedPublic

Authored by arsenm on Sep 2 2019, 12:51 AM.

Details

Reviewers
tstellar
nhaehnle
kerbowa
Summary

This is mostly for the benefit of patterns which use 16-bit constants.

Diff Detail

Event Timeline

arsenm created this revision.Sep 2 2019, 12:51 AM
Herald added subscribers: Petar.Avramovic, t-tye, tpr and 6 others. · View Herald TranscriptSep 2 2019, 12:51 AM
kerbowa accepted this revision.Sep 3 2019, 12:35 PM

LGTM

This revision is now accepted and ready to land.Sep 3 2019, 12:35 PM
arsenm closed this revision.Sep 4 2019, 9:18 AM

r370921

Revision Contents

Diff 218301

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 241 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder(G_BITCAST) getActionDefinitionsBuilder(G_BITCAST)
.legalForCartesianProduct({S32, V2S16}) .legalForCartesianProduct({S32, V2S16})
.legalForCartesianProduct({S64, V2S32, V4S16}) .legalForCartesianProduct({S64, V2S32, V4S16})
.legalForCartesianProduct({V2S64, V4S32}) .legalForCartesianProduct({V2S64, V4S32})
// Don't worry about the size constraint. // Don't worry about the size constraint.
.legalIf(all(isPointer(0), isPointer(1))); .legalIf(all(isPointer(0), isPointer(1)));
if (ST.has16BitInsts()) {
getActionDefinitionsBuilder(G_FCONSTANT) getActionDefinitionsBuilder(G_FCONSTANT)
.legalFor({S32, S64, S16}) .legalFor({S32, S64, S16})
.clampScalar(0, S16, S64); .clampScalar(0, S16, S64);
} else {
getActionDefinitionsBuilder(G_FCONSTANT)
.legalFor({S32, S64})
.clampScalar(0, S32, S64);
}
getActionDefinitionsBuilder(G_IMPLICIT_DEF) getActionDefinitionsBuilder(G_IMPLICIT_DEF)
.legalFor({S1, S32, S64, V2S32, V4S32, V2S16, V4S16, GlobalPtr, .legalFor({S1, S32, S64, S16, V2S32, V4S32, V2S16, V4S16, GlobalPtr,
ConstantPtr, LocalPtr, FlatPtr, PrivatePtr}) ConstantPtr, LocalPtr, FlatPtr, PrivatePtr})
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0)) .moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
.clampScalarOrElt(0, S32, S512) .clampScalarOrElt(0, S32, S512)
.legalIf(isMultiple32(0)) .legalIf(isMultiple32(0))
.widenScalarToNextPow2(0, 32) .widenScalarToNextPow2(0, 32)
.clampMaxNumElements(0, S32, 16); .clampMaxNumElements(0, S32, 16);
// FIXME: i1 operands to intrinsics should always be legal, but other i1 // FIXME: i1 operands to intrinsics should always be legal, but other i1
// values may not be legal. We need to figure out how to distinguish // values may not be legal. We need to figure out how to distinguish
// between these two scenarios. // between these two scenarios.
getActionDefinitionsBuilder(G_CONSTANT) getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({S1, S32, S64, GlobalPtr, .legalFor({S1, S32, S64, S16, GlobalPtr,
LocalPtr, ConstantPtr, PrivatePtr, FlatPtr }) LocalPtr, ConstantPtr, PrivatePtr, FlatPtr })
.clampScalar(0, S32, S64) .clampScalar(0, S32, S64)
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.legalIf(isPointer(0)); .legalIf(isPointer(0));
setAction({G_FRAME_INDEX, PrivatePtr}, Legal); setAction({G_FRAME_INDEX, PrivatePtr}, Legal);
auto &FPOpActions = getActionDefinitionsBuilder( auto &FPOpActions = getActionDefinitionsBuilder(
▲ Show 20 Lines • Show All 1,262 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; The G_SEXT_INREG doesn't lower here because G_TRUNC is both illegal and ; The G_SEXT_INREG doesn't lower here because G_TRUNC is both illegal and
; unable to legalize. This prevents further legalization. ; unable to legalize. This prevents further legalization.
; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16 ; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>) ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]](<2 x s16>)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[ZEXT]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[ZEXT]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16) ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[ZEXT1]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[ZEXT1]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16) ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC2]](s16) ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC1]](s16)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT]], [[ZEXT2]](s32) ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT]], [[ZEXT2]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s16) ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s16)
; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC3]](s16) ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC2]](s16)
; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[ZEXT3]](s32) ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[ZEXT3]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC4]](s16), [[TRUNC5]](s16) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC3]](s16), [[TRUNC4]](s16)
; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_TRUNC %0 %1:_(<2 x s8>) = G_TRUNC %0
%2:_(<2 x s16>) = G_SEXT %1 %2:_(<2 x s16>) = G_SEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
Show All 23 Lines

test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
--- ---
name: test_zext_trunc_v2s32_to_v2s8_to_v2s16 name: test_zext_trunc_v2s32_to_v2s8_to_v2s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s8_to_v2s16 ; CHECK-LABEL: name: test_zext_trunc_v2s32_to_v2s8_to_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16) ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>)
; CHECK: [[TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[COPY]](<2 x s32>) ; CHECK: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[TRUNC]], [[BUILD_VECTOR]]
; CHECK: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[TRUNC1]], [[BUILD_VECTOR]]
; CHECK: $vgpr0 = COPY [[AND]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[AND]](<2 x s16>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_TRUNC %0 %1:_(<2 x s8>) = G_TRUNC %0
%2:_(<2 x s16>) = G_ZEXT %1 %2:_(<2 x s16>) = G_ZEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
Show All 25 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 Lines bb.0:
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_ashr_s16_i8 ; VI-LABEL: name: test_ashr_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16) ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_ashr_s16_i8 ; GFX9-LABEL: name: test_ashr_s16_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16) ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s16) = G_ASHR %2, %3 %4:_(s16) = G_ASHR %2, %3
Show All 18 Lines bb.0:
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s32) ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s32)
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_ashr_i8_i8 ; VI-LABEL: name: test_ashr_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C1]](s16)
; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32) ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C1]](s16)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[TRUNC3]](s16)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC3]](s16)
; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s16) ; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_ashr_i8_i8 ; GFX9-LABEL: name: test_ashr_i8_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C1]](s16)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32) ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C1]](s16)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[TRUNC3]](s16)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC3]](s16)
; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s16) ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_ASHR %2, %3 %4:_(s8) = G_ASHR %2, %3
▲ Show 20 Lines • Show All 1,322 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
--- ---
name: test_constant_s16 name: test_constant_s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_constant_s16 ; CHECK-LABEL: name: test_constant_s16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; CHECK: $vgpr0 = COPY [[C]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s16) = G_CONSTANT i16 5 %0:_(s16) = G_CONSTANT i16 5
%1:_(s32) = G_ANYEXT %0 %1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_constant_s128 name: test_constant_s128
body: | body: |
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir

Show First 20 Lines • Show All 450 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_v2s16_idx2_i32 ; CHECK-LABEL: name: extract_vector_elt_v2s16_idx2_i32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[DEF]](s32) ; CHECK: $vgpr0 = COPY [[DEF]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 2 %1:_(s32) = G_CONSTANT i32 2
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1 %2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
▲ Show 20 Lines • Show All 196 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir

Show First 20 Lines • Show All 603 Lines • ▼ Show 20 Lines
--- ---
name: test_extract_s8_s16_offset1 name: test_extract_s8_s16_offset1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s16_offset1 ; CHECK-LABEL: name: test_extract_s8_s16_offset1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C]](s16)
; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s8) = G_EXTRACT %1, 1 %2:_(s8) = G_EXTRACT %1, 1
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: test_extract_s8_s16_offset8 name: test_extract_s8_s16_offset8
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s16_offset8 ; CHECK-LABEL: name: test_extract_s8_s16_offset8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C]](s16)
; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s8) = G_EXTRACT %1, 8 %2:_(s8) = G_EXTRACT %1, 8
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
--- ---
name: test_extract_s1_s8_offset2 name: test_extract_s1_s8_offset2
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s1_s8_offset2 ; CHECK-LABEL: name: test_extract_s1_s8_offset2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C]](s16)
; CHECK: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0 %1:_(s8) = G_TRUNC %0
%2:_(s1) = G_EXTRACT %1, 2 %2:_(s1) = G_EXTRACT %1, 2
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
▲ Show 20 Lines • Show All 139 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
... ...
--- ---
name: test_fcmp_s16 name: test_fcmp_s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX7-LABEL: name: test_fcmp_s16 ; GFX7-LABEL: name: test_fcmp_s16
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX7: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX7: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) ; GFX7: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[C]](s16)
; GFX7: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) ; GFX7: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; GFX7: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[FPEXT]](s32), [[FPEXT1]] ; GFX7: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[FPEXT]](s32), [[FPEXT1]]
; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[TRUNC]], [[TRUNC1]] ; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C]], [[TRUNC]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16) ; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX7: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX7: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: test_fcmp_s16 ; GFX8-LABEL: name: test_fcmp_s16
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[TRUNC]](s16), [[TRUNC1]] ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s16), [[TRUNC]]
; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[TRUNC]], [[TRUNC1]] ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C]], [[TRUNC]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_fcmp_s16 ; GFX9-LABEL: name: test_fcmp_s16
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[TRUNC]](s16), [[TRUNC1]] ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s16), [[TRUNC]]
; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[TRUNC]], [[TRUNC1]] ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[FCMP]](s1), [[C]], [[TRUNC]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s16) = G_CONSTANT i16 0 %0:_(s16) = G_CONSTANT i16 0
%1:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr0
%2:_(s16) = G_TRUNC %1 %2:_(s16) = G_TRUNC %1
%3:_(s1) = G_FCMP floatpred(oeq), %0, %2 %3:_(s1) = G_FCMP floatpred(oeq), %0, %2
%4:_(s16) = G_SELECT %3, %0, %2 %4:_(s16) = G_SELECT %3, %0, %2
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
▲ Show 20 Lines • Show All 295 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s
--- ---
name: test_fconstant_s32 name: test_fconstant_s32
body: | body: |
bb.0: bb.0:
; SI-LABEL: name: test_fconstant_s32 ; GCN-LABEL: name: test_fconstant_s32
; SI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 ; GCN: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; SI: $vgpr0 = COPY [[C]](s32) ; GCN: $vgpr0 = COPY [[C]](s32)
; VI-LABEL: name: test_fconstant_s32
; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; VI: $vgpr0 = COPY [[C]](s32)
%0:_(s32) = G_FCONSTANT float 1.0 %0:_(s32) = G_FCONSTANT float 1.0
$vgpr0 = COPY %0 $vgpr0 = COPY %0
... ...
--- ---
name: test_fconstant_s64 name: test_fconstant_s64
body: | body: |
bb.0: bb.0:
; SI-LABEL: name: test_fconstant_s64 ; GCN-LABEL: name: test_fconstant_s64
; SI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00 ; GCN: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
; SI: $vgpr0_vgpr1 = COPY [[C]](s64) ; GCN: $vgpr0_vgpr1 = COPY [[C]](s64)
; VI-LABEL: name: test_fconstant_s64
; VI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
; VI: $vgpr0_vgpr1 = COPY [[C]](s64)
%0:_(s64) = G_FCONSTANT double 1.0 %0:_(s64) = G_FCONSTANT double 1.0
$vgpr0_vgpr1 = COPY %0 $vgpr0_vgpr1 = COPY %0
... ...
--- ---
name: test_fconstant_s16 name: test_fconstant_s16
body: | body: |
bb.0: bb.0:
; SI-LABEL: name: test_fconstant_s16 ; GCN-LABEL: name: test_fconstant_s16
; SI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 ; GCN: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C]](s32) ; GCN: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16) ; GCN: $vgpr0 = COPY [[ANYEXT]](s32)
; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_fconstant_s16
; VI: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s16) = G_FCONSTANT half 1.0 %0:_(s16) = G_FCONSTANT half 1.0
%1:_(s32) = G_ANYEXT %0 %1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...

test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s
--- ---
name: test_copysign_s16_s16 name: test_copysign_s16_s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_copysign_s16_s16 ; SI-LABEL: name: test_copysign_s16_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32) ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC1]]
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]] ; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI: $vgpr0 = COPY [[ANYEXT]](s32) ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s16 ; VI-LABEL: name: test_copysign_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32) ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC1]]
; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]] ; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s16 ; GFX9-LABEL: name: test_copysign_s16_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32) ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC1]]
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]] ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
%4:_(s16) = G_FCOPYSIGN %2, %3 %4:_(s16) = G_FCOPYSIGN %2, %3
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_copysign_s16_s32 ; SI-LABEL: name: test_copysign_s16_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]] ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]] ; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI: $vgpr0 = COPY [[ANYEXT]](s32) ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s32 ; VI-LABEL: name: test_copysign_s16_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]] ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]] ; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s32 ; GFX9-LABEL: name: test_copysign_s16_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]] ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]] ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_FCOPYSIGN %2, %1 %3:_(s16) = G_FCOPYSIGN %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1_vgpr2 liveins: $vgpr0, $vgpr1_vgpr2
; SI-LABEL: name: test_copysign_s16_s64 ; SI-LABEL: name: test_copysign_s16_s64
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2 ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; SI: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64) ; SI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC3]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC1]](s32)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64) ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[TRUNC1]] ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]] ; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI: $vgpr0 = COPY [[ANYEXT]](s32) ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s64 ; VI-LABEL: name: test_copysign_s16_s64
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2 ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; VI: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64) ; VI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC3]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC1]](s32)
; VI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64) ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[TRUNC1]] ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]] ; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s64 ; GFX9-LABEL: name: test_copysign_s16_s64
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2 ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; GFX9: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC3]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC1]](s32)
; GFX9: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64) ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[TRUNC1]] ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]] ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s64) = COPY $vgpr1_vgpr2 %1:_(s64) = COPY $vgpr1_vgpr2
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_FCOPYSIGN %2, %1 %3:_(s16) = G_FCOPYSIGN %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...
--- ---
name: test_copysign_v2s16_v2s16 name: test_copysign_v2s16_v2s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_copysign_v2s16_v2s16 ; SI-LABEL: name: test_copysign_v2s16_v2s16
; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16) ; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC1]](s16)
; SI: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR1]] ; SI: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; SI: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR]] ; SI: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR]]
; SI: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]] ; SI: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]]
; SI: $vgpr0 = COPY [[OR]](<2 x s16>) ; SI: $vgpr0 = COPY [[OR]](<2 x s16>)
; VI-LABEL: name: test_copysign_v2s16_v2s16 ; VI-LABEL: name: test_copysign_v2s16_v2s16
; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16) ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC1]](s16)
; VI: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR1]] ; VI: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; VI: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR]] ; VI: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR]]
; VI: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]] ; VI: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]]
; VI: $vgpr0 = COPY [[OR]](<2 x s16>) ; VI: $vgpr0 = COPY [[OR]](<2 x s16>)
; GFX9-LABEL: name: test_copysign_v2s16_v2s16 ; GFX9-LABEL: name: test_copysign_v2s16_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16) ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C1]](s16), [[C1]](s16)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC1]](s16)
; GFX9: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR1]] ; GFX9: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR1]]
; GFX9: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR]] ; GFX9: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[COPY]], [[BUILD_VECTOR]]
; GFX9: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]] ; GFX9: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[AND]], [[AND1]]
; GFX9: $vgpr0 = COPY [[OR]](<2 x s16>) ; GFX9: $vgpr0 = COPY [[OR]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1 %1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_FCOPYSIGN %0, %1 %2:_(<2 x s16>) = G_FCOPYSIGN %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
▲ Show 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_copysign_s16_s32_flags ; SI-LABEL: name: test_copysign_s16_s32_flags
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]] ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; SI: %3:_(s16) = nnan G_OR [[AND]], [[AND1]] ; SI: %3:_(s16) = nnan G_OR [[AND]], [[AND1]]
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16) ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; SI: $vgpr0 = COPY [[ANYEXT]](s32) ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s32_flags ; VI-LABEL: name: test_copysign_s16_s32_flags
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]] ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: %3:_(s16) = nnan G_OR [[AND]], [[AND1]] ; VI: %3:_(s16) = nnan G_OR [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s32_flags ; GFX9-LABEL: name: test_copysign_s16_s32_flags
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]] ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: %3:_(s16) = nnan G_OR [[AND]], [[AND1]] ; GFX9: %3:_(s16) = nnan G_OR [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = nnan G_FCOPYSIGN %2, %1 %3:_(s16) = nnan G_FCOPYSIGN %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...

test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
... ...
--- ---
name: test_icmp_s16 name: test_icmp_s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX7-LABEL: name: test_icmp_s16 ; GFX7-LABEL: name: test_icmp_s16
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX7: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; GFX7: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C1]](s32), [[AND]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]] ; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16) ; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX7: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX7: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: test_icmp_s16 ; GFX8-LABEL: name: test_icmp_s16
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[TRUNC]](s16), [[TRUNC1]] ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s16), [[TRUNC]]
; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]] ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_icmp_s16 ; GFX9-LABEL: name: test_icmp_s16
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[TRUNC]](s16), [[TRUNC1]] ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s16), [[TRUNC]]
; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]] ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s16) = G_CONSTANT i16 0 %0:_(s16) = G_CONSTANT i16 0
%1:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr0
%2:_(s16) = G_TRUNC %1 %2:_(s16) = G_TRUNC %1
%3:_(s1) = G_ICMP intpred(ne), %0, %2 %3:_(s1) = G_ICMP intpred(ne), %0, %2
%4:_(s16) = G_SELECT %3, %0, %2 %4:_(s16) = G_SELECT %3, %0, %2
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
▲ Show 20 Lines • Show All 709 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
--- ---
name: test_implicit_def_s16 name: test_implicit_def_s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_implicit_def_s16 ; CHECK-LABEL: name: test_implicit_def_s16
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32) ; CHECK: $vgpr0 = COPY [[DEF]](s32)
; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s16) = G_IMPLICIT_DEF %0:_(s16) = G_IMPLICIT_DEF
%1:_(s32) = G_ANYEXT %0 %1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_implicit_def_s32 name: test_implicit_def_s32
body: | body: |
▲ Show 20 Lines • Show All 505 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir

Show First 20 Lines • Show All 212 Lines • ▼ Show 20 Lines bb.0:
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_lshr_s16_i8 ; VI-LABEL: name: test_lshr_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16) ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_lshr_s16_i8 ; GFX9-LABEL: name: test_lshr_s16_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16) ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s16) = G_LSHR %2, %3 %4:_(s16) = G_LSHR %2, %3
Show All 16 Lines bb.0:
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_lshr_i8_i8 ; VI-LABEL: name: test_lshr_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[AND]](s16) ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_lshr_i8_i8 ; GFX9-LABEL: name: test_lshr_i8_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[AND]](s16) ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_LSHR %2, %3 %4:_(s8) = G_LSHR %2, %3
▲ Show 20 Lines • Show All 1,282 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir

Show All 15 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6 ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7 ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]] ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY8]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]] ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC]] ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32) ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[AND4]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY10]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC4]] ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[TRUNC]] ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32) ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]] ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[AND7]](s32) ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY12]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32) ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC6]] ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32) ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[TRUNC]] ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C]]
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C6]](s32) ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]] ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32) ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]] ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[AND10]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND9]], [[TRUNC8]]
; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16), [[OR2]](s16), [[OR3]](s16) ; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16), [[OR2]](s16), [[OR3]](s16)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](p1) ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](p1)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2 %2:_(s32) = COPY $vgpr2
%3:_(s32) = COPY $vgpr3 %3:_(s32) = COPY $vgpr3
%4:_(s32) = COPY $vgpr4 %4:_(s32) = COPY $vgpr4
%5:_(s32) = COPY $vgpr5 %5:_(s32) = COPY $vgpr5
Show All 14 Lines
--- ---
name: test_merge_s16_s8_s8 name: test_merge_s16_s8_s8
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_merge_s16_s8_s8 ; CHECK-LABEL: name: test_merge_s16_s8_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]] ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s8) = G_CONSTANT i8 0 %0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1 %1:_(s8) = G_CONSTANT i8 1
%2:_(s16) = G_MERGE_VALUES %0, %1 %2:_(s16) = G_MERGE_VALUES %0, %1
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: test_merge_s24_s8_s8_s8 name: test_merge_s24_s8_s8_s8
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_merge_s24_s8_s8_s8 ; CHECK-LABEL: name: test_merge_s24_s8_s8_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C3]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C5]] ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]] ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC]] ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C7]](s32) ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]] ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]] ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[AND4]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC4]]
; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16) ; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MV]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[MV]](s32)
; CHECK: $vgpr0 = COPY [[COPY4]](s32) ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
%0:_(s8) = G_CONSTANT i8 0 %0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1 %1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_CONSTANT i8 2 %2:_(s8) = G_CONSTANT i8 2
%3:_(s24) = G_MERGE_VALUES %0, %1, %2 %3:_(s24) = G_MERGE_VALUES %0, %1, %2
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...
--- ---
name: test_merge_s32_s8_s8_s8_s8 name: test_merge_s32_s8_s8_s8_s8
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_merge_s32_s8_s8_s8_s8 ; CHECK-LABEL: name: test_merge_s32_s8_s8_s8_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C5]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C6]] ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]] ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC]] ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32) ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]] ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]] ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[AND4]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC4]]
; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16) ; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16)
; CHECK: $vgpr0 = COPY [[MV]](s32) ; CHECK: $vgpr0 = COPY [[MV]](s32)
%0:_(s8) = G_CONSTANT i8 0 %0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1 %1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_CONSTANT i8 2 %2:_(s8) = G_CONSTANT i8 2
%3:_(s8) = G_CONSTANT i8 3 %3:_(s8) = G_CONSTANT i8 3
%4:_(s32) = G_MERGE_VALUES %0, %1, %2, %3 %4:_(s32) = G_MERGE_VALUES %0, %1, %2, %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines bb.0:
; CHECK-LABEL: name: test_merge_s24_s4_s4_s4_s4_s4_s4 ; CHECK-LABEL: name: test_merge_s24_s4_s4_s4_s4_s4_s4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; CHECK: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C6]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C6]]
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C8]]
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C9]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]] ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C10]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C8]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C9]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[AND3]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[COPY2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC3]] ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC2]]
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C11]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C8]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C9]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[AND5]](s32) ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY4]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC4]] ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC3]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[TRUNC]] ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C6]]
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C8]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]] ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[AND8]](s32) ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY6]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32) ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND7]], [[TRUNC6]] ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C13]](s32) ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C8]] ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC6]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32) ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]] ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C7]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[AND10]](s32) ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32) ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC7]] ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC7]]
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C8]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[AND12]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC8]]
; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR2]](s16), [[OR5]](s16) ; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR2]](s16), [[OR5]](s16)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s24) = G_TRUNC [[MV]](s32) ; CHECK: [[TRUNC8:%[0-9]+]]:_(s24) = G_TRUNC [[MV]](s32)
; CHECK: S_NOP 0, implicit [[TRUNC9]](s24) ; CHECK: S_NOP 0, implicit [[TRUNC8]](s24)
%0:_(s4) = G_CONSTANT i4 0 %0:_(s4) = G_CONSTANT i4 0
%1:_(s4) = G_CONSTANT i4 1 %1:_(s4) = G_CONSTANT i4 1
%2:_(s4) = G_CONSTANT i4 2 %2:_(s4) = G_CONSTANT i4 2
%3:_(s4) = G_CONSTANT i4 3 %3:_(s4) = G_CONSTANT i4 3
%4:_(s4) = G_CONSTANT i4 4 %4:_(s4) = G_CONSTANT i4 4
%5:_(s4) = G_CONSTANT i4 5 %5:_(s4) = G_CONSTANT i4 5
%6:_(s24) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5 %6:_(s24) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5
S_NOP 0, implicit %6 S_NOP 0, implicit %6
... ...
--- ---
name: test_merge_s28_s4_s4_s4_s4_s4_s4_s4 name: test_merge_s28_s4_s4_s4_s4_s4_s4_s4
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_merge_s28_s4_s4_s4_s4_s4_s4_s4 ; CHECK-LABEL: name: test_merge_s28_s4_s4_s4_s4_s4_s4_s4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C7]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C7]]
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C9]]
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C10]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C8]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]] ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C11]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C10]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C8]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[AND3]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[COPY2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC3]] ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC2]]
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C12]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C10]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C8]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[AND5]](s32) ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY4]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC4]] ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC3]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[TRUNC]] ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C10]] ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C8]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[AND8]](s32) ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY6]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32) ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND7]], [[TRUNC6]] ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C14]](s32) ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C8]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C9]] ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C9]](s32)
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C6]](s32) ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C10]] ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC6]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[AND10]](s32) ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32) ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C8]]
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC7]] ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C10]](s32)
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C15]](s32) ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC7]]
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C9]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C10]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[AND12]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC8]]
; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR2]](s16), [[OR5]](s16) ; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR2]](s16), [[OR5]](s16)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s28) = G_TRUNC [[MV]](s32) ; CHECK: [[TRUNC8:%[0-9]+]]:_(s28) = G_TRUNC [[MV]](s32)
; CHECK: S_NOP 0, implicit [[TRUNC9]](s28) ; CHECK: S_NOP 0, implicit [[TRUNC8]](s28)
%0:_(s4) = G_CONSTANT i4 0 %0:_(s4) = G_CONSTANT i4 0
%1:_(s4) = G_CONSTANT i4 1 %1:_(s4) = G_CONSTANT i4 1
%2:_(s4) = G_CONSTANT i4 2 %2:_(s4) = G_CONSTANT i4 2
%3:_(s4) = G_CONSTANT i4 3 %3:_(s4) = G_CONSTANT i4 3
%4:_(s4) = G_CONSTANT i4 4 %4:_(s4) = G_CONSTANT i4 4
%5:_(s4) = G_CONSTANT i4 5 %5:_(s4) = G_CONSTANT i4 5
%6:_(s4) = G_CONSTANT i4 6 %6:_(s4) = G_CONSTANT i4 6
%7:_(s28) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6 %7:_(s28) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6
Show All 27 Lines bb.0:
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9 ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11 ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C12]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C12]]
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C14]]
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C15]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C13]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]] ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC]] ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C12]]
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C14]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C15]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C13]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[AND4]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC4]] ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[TRUNC]] ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C12]]
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C14]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C5]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C15]] ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C13]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[AND7]](s32) ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32) ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC6]] ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[C6]](s32) ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[C6]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[TRUNC]] ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C12]]
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C14]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C7]](s32) ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C15]] ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C13]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[AND10]](s32) ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32) ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND9]], [[TRUNC8]] ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[C8]](s32) ; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[C8]](s32)
; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC9]], [[TRUNC]] ; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C12]]
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C14]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C9]](s32) ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C15]] ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C13]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[AND13]](s32) ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32) ; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC10]] ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[C10]](s32) ; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[C10]](s32)
; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[TRUNC11]], [[TRUNC]] ; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C12]]
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C20]](s32)
; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C14]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C11]](s32) ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C15]] ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C13]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[AND16]](s32) ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
; CHECK: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32) ; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND15]], [[TRUNC12]] ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16), [[OR2]](s16), [[OR3]](s16), [[OR4]](s16), [[OR5]](s16) ; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16), [[OR2]](s16), [[OR3]](s16), [[OR4]](s16), [[OR5]](s16)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96) ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s8) = G_CONSTANT i8 0 %0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1 %1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_CONSTANT i8 2 %2:_(s8) = G_CONSTANT i8 2
%3:_(s8) = G_CONSTANT i8 3 %3:_(s8) = G_CONSTANT i8 3
%4:_(s8) = G_CONSTANT i8 4 %4:_(s8) = G_CONSTANT i8 4
%5:_(s8) = G_CONSTANT i8 5 %5:_(s8) = G_CONSTANT i8 5
%6:_(s8) = G_CONSTANT i8 6 %6:_(s8) = G_CONSTANT i8 6
%7:_(s8) = G_CONSTANT i8 7 %7:_(s8) = G_CONSTANT i8 7
%9:_(s8) = G_CONSTANT i8 8 %9:_(s8) = G_CONSTANT i8 8
%10:_(s8) = G_CONSTANT i8 9 %10:_(s8) = G_CONSTANT i8 9
%11:_(s8) = G_CONSTANT i8 10 %11:_(s8) = G_CONSTANT i8 10
%12:_(s8) = G_CONSTANT i8 11 %12:_(s8) = G_CONSTANT i8 11
%13:_(s96) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6, %7, %9, %10, %11, %12 %13:_(s96) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6, %7, %9, %10, %11, %12
$vgpr0_vgpr1_vgpr2 = COPY %13 $vgpr0_vgpr1_vgpr2 = COPY %13
... ...
--- ---
name: test_merge_s96_s16_s16_s16_s16_s16_s16 name: test_merge_s96_s16_s16_s16_s16_s16_s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_merge_s96_s16_s16_s16_s16_s16_s16 ; CHECK-LABEL: name: test_merge_s96_s16_s16_s16_s16_s16_s16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32) ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32) ; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 5
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[C]](s16), [[C1]](s16), [[C2]](s16), [[C3]](s16), [[C4]](s16), [[C5]](s16)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[C5]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96) ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s16) = G_CONSTANT i16 0 %0:_(s16) = G_CONSTANT i16 0
%1:_(s16) = G_CONSTANT i16 1 %1:_(s16) = G_CONSTANT i16 1
%2:_(s16) = G_CONSTANT i16 2 %2:_(s16) = G_CONSTANT i16 2
%3:_(s16) = G_CONSTANT i16 3 %3:_(s16) = G_CONSTANT i16 3
%4:_(s16) = G_CONSTANT i16 4 %4:_(s16) = G_CONSTANT i16 4
%5:_(s16) = G_CONSTANT i16 5 %5:_(s16) = G_CONSTANT i16 5
%8:_(s96) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5 %8:_(s96) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5
$vgpr0_vgpr1_vgpr2 = COPY %8 $vgpr0_vgpr1_vgpr2 = COPY %8
... ...
--- ---
name: test_merge_s56_s8_s8_s8_s8_s8_s8_s8 name: test_merge_s56_s8_s8_s8_s8_s8_s8_s8
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_merge_s56_s8_s8_s8_s8_s8_s8_s8 ; CHECK-LABEL: name: test_merge_s56_s8_s8_s8_s8_s8_s8_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C7]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C7]]
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C8]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C9]] ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C10]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C9]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]] ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32) ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC]] ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C10]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C9]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[AND4]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC4]] ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[TRUNC]] ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C5]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C10]] ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C9]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[AND7]](s32) ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32) ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC6]] ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[C6]](s32) ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[C6]](s32)
; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[TRUNC]] ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C13]](s32) ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]] ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[DEF]](s32) ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C10]] ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[AND10]](s32)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND9]], [[TRUNC8]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16), [[OR2]](s16), [[OR3]](s16) ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16), [[OR2]](s16), [[OR3]](s16)
; CHECK: [[TRUNC9:%[0-9]+]]:_(s56) = G_TRUNC [[MV]](s64) ; CHECK: [[TRUNC8:%[0-9]+]]:_(s56) = G_TRUNC [[MV]](s64)
; CHECK: S_NOP 0, implicit [[TRUNC9]](s56) ; CHECK: S_NOP 0, implicit [[TRUNC8]](s56)
%0:_(s8) = G_CONSTANT i8 0 %0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1 %1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_CONSTANT i8 2 %2:_(s8) = G_CONSTANT i8 2
%3:_(s8) = G_CONSTANT i8 3 %3:_(s8) = G_CONSTANT i8 3
%4:_(s8) = G_CONSTANT i8 4 %4:_(s8) = G_CONSTANT i8 4
%5:_(s8) = G_CONSTANT i8 5 %5:_(s8) = G_CONSTANT i8 5
%6:_(s8) = G_CONSTANT i8 6 %6:_(s8) = G_CONSTANT i8 6
%7:_(s56) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6 %7:_(s56) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Lines bb.0:
%4:_(s68) = G_MERGE_VALUES %0, %1, %2, %3 %4:_(s68) = G_MERGE_VALUES %0, %1, %2, %3
S_NOP 0, implicit %4 S_NOP 0, implicit %4
... ...
--- ---
name: test_merge_p3_s16_s16 name: test_merge_p3_s16_s16
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_merge_p3_s16_s16 ; CHECK-LABEL: name: test_merge_p3_s16_s16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[MV:%[0-9]+]]:_(p3) = G_MERGE_VALUES [[C]](s16), [[C1]](s16)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; CHECK: [[MV:%[0-9]+]]:_(p3) = G_MERGE_VALUES [[TRUNC]](s16), [[TRUNC1]](s16)
; CHECK: $vgpr0 = COPY [[MV]](p3) ; CHECK: $vgpr0 = COPY [[MV]](p3)
%0:_(s16) = G_CONSTANT i16 0 %0:_(s16) = G_CONSTANT i16 0
%1:_(s16) = G_CONSTANT i16 1 %1:_(s16) = G_CONSTANT i16 1
%2:_(p3) = G_MERGE_VALUES %0, %1 %2:_(p3) = G_MERGE_VALUES %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...

test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir

Show First 20 Lines • Show All 1,253 Lines • ▼ Show 20 Linesbody: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1 ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
; CHECK: G_BR %bb.2 ; CHECK: G_BR %bb.2
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
; CHECK: G_BR %bb.2 ; CHECK: G_BR %bb.2
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY2]](s32), %bb.0, [[COPY3]](s32), %bb.1 ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY2]](s32), %bb.0, [[DEF]](s32), %bb.1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[PHI]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32) ; CHECK: $vgpr0 = COPY [[AND]](s32)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31 ; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0: bb.0:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
▲ Show 20 Lines • Show All 127 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
name: test_select_s16 name: test_select_s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_select_s16 ; CHECK-LABEL: name: test_select_s16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32) ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = G_CONSTANT i32 0 %0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr0
%2:_(s1) = G_ICMP intpred(ne), %0, %1 %2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s16) = G_CONSTANT i16 1 %3:_(s16) = G_CONSTANT i16 1
%4:_(s16) = G_CONSTANT i16 2 %4:_(s16) = G_CONSTANT i16 2
▲ Show 20 Lines • Show All 1,107 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Lines bb.0:
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32) ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_shl_s16_i8 ; VI-LABEL: name: test_shl_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16) ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_shl_s16_i8 ; GFX9-LABEL: name: test_shl_s16_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16) ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s16) = G_SHL %2, %3 %4:_(s16) = G_SHL %2, %3
Show All 15 Lines bb.0:
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32) ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_shl_i8_i8 ; VI-LABEL: name: test_shl_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_shl_i8_i8 ; GFX9-LABEL: name: test_shl_i8_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_SHL %2, %3 %4:_(s8) = G_SHL %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
▲ Show 20 Lines • Show All 508 Lines • ▼ Show 20 Lines bb.0:
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32) ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_shl_s7_s7 ; VI-LABEL: name: test_shl_s7_s7
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_shl_s7_s7 ; GFX9-LABEL: name: test_shl_s7_s7
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 127
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[AND]](s16)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0 %2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1 %3:_(s7) = G_TRUNC %1
%4:_(s7) = G_SHL %2, %3 %4:_(s7) = G_SHL %2, %3
%5:_(s32) = G_ANYEXT %4 %5:_(s32) = G_ANYEXT %4
▲ Show 20 Lines • Show All 811 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines bb.0:
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]] ; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASHR]], [[ASHR1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_smax_s8 ; VI-LABEL: name: test_smax_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16) ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC1]](s16) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16)
; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[TRUNC3]](s16)
; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[TRUNC3]](s16)
; VI: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[ASHR]], [[ASHR1]] ; VI: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[ASHR]], [[ASHR1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMAX]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMAX]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_smax_s8 ; GFX9-LABEL: name: test_smax_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16) ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC1]](s16) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[TRUNC3]](s16)
; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[TRUNC3]](s16)
; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[ASHR]], [[ASHR1]] ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[ASHR]], [[ASHR1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMAX]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMAX]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_SMAX %2, %3 %4:_(s8) = G_SMAX %2, %3
▲ Show 20 Lines • Show All 404 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines bb.0:
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]] ; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASHR]], [[ASHR1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_smin_s8 ; VI-LABEL: name: test_smin_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16) ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC1]](s16) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16)
; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[TRUNC3]](s16)
; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[TRUNC3]](s16)
; VI: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[ASHR]], [[ASHR1]] ; VI: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[ASHR]], [[ASHR1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_smin_s8 ; GFX9-LABEL: name: test_smin_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16) ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC1]](s16) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[C]](s16)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[TRUNC3]](s16)
; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SHL1]], [[TRUNC3]](s16)
; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[ASHR]], [[ASHR1]] ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[ASHR]], [[ASHR1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_SMIN %2, %3 %4:_(s8) = G_SMIN %2, %3
▲ Show 20 Lines • Show All 404 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines bb.0:
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]] ; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_umax_s8 ; VI-LABEL: name: test_umax_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
; VI: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[AND]], [[AND1]] ; VI: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_umax_s8 ; GFX9-LABEL: name: test_umax_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
; GFX9: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[AND]], [[AND1]] ; GFX9: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_UMAX %2, %3 %4:_(s8) = G_UMAX %2, %3
▲ Show 20 Lines • Show All 383 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines bb.0:
; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; SI: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]] ; SI: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32) ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
; SI: $vgpr0 = COPY [[COPY4]](s32) ; SI: $vgpr0 = COPY [[COPY4]](s32)
; VI-LABEL: name: test_umin_s8 ; VI-LABEL: name: test_umin_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
; VI: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[AND]], [[AND1]] ; VI: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMIN]](s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMIN]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_umin_s8 ; GFX9-LABEL: name: test_umin_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]] ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[AND]], [[AND1]] ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMIN]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMIN]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0 %2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1 %3:_(s8) = G_TRUNC %1
%4:_(s8) = G_UMIN %2, %3 %4:_(s8) = G_UMIN %2, %3
▲ Show 20 Lines • Show All 383 Lines • Show Last 20 Lines