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Differential D67042

AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOAD
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Authored by arsenm on Aug 31 2019, 1:01 PM.

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Reviewers
tstellar
nhaehnle
kerbowa

Diff Detail

Event Timeline

arsenm created this revision.Aug 31 2019, 1:01 PM
Herald added subscribers: Petar.Avramovic, t-tye, tpr and 6 others. · View Herald TranscriptAug 31 2019, 1:01 PM
kerbowa accepted this revision.Sep 9 2019, 8:51 AM

LGTM

This revision is now accepted and ready to land.Sep 9 2019, 8:51 AM
arsenm closed this revision.Sep 10 2019, 9:41 AM

r371536

Revision Contents

PathSize
lib/
Target/
AMDGPU/
4 lines
10 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
98 lines
97 lines

Diff 218234

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 778 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
} }
auto &ExtLoads = getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD}) auto &ExtLoads = getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
.legalForTypesWithMemDesc({{S32, GlobalPtr, 8, 8}, .legalForTypesWithMemDesc({{S32, GlobalPtr, 8, 8},
{S32, GlobalPtr, 16, 2 * 8}, {S32, GlobalPtr, 16, 2 * 8},
{S32, LocalPtr, 8, 8}, {S32, LocalPtr, 8, 8},
{S32, LocalPtr, 16, 16}, {S32, LocalPtr, 16, 16},
{S32, PrivatePtr, 8, 8}, {S32, PrivatePtr, 8, 8},
{S32, PrivatePtr, 16, 16}}); {S32, PrivatePtr, 16, 16},
{S32, ConstantPtr, 8, 8},
{S32, ConstantPtr, 16, 2 * 8}});
if (ST.hasFlatAddressSpace()) { if (ST.hasFlatAddressSpace()) {
ExtLoads.legalForTypesWithMemDesc( ExtLoads.legalForTypesWithMemDesc(
{{S32, FlatPtr, 8, 8}, {S32, FlatPtr, 16, 16}}); {{S32, FlatPtr, 8, 8}, {S32, FlatPtr, 16, 16}});
} }
ExtLoads.clampScalar(0, S32, S32) ExtLoads.clampScalar(0, S32, S32)
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.unsupportedIfMemSizeNotPow2() .unsupportedIfMemSizeNotPow2()
▲ Show 20 Lines • Show All 975 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 413 Lines • ▼ Show 20 Lines const InstructionMapping &VSMapping = getInstructionMapping(
3, 4, getOperandsMapping( 3, 4, getOperandsMapping(
{AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), {AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size)}), AMDGPU::getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size)}),
3); // Num Operands 3); // Num Operands
AltMappings.push_back(&VSMapping); AltMappings.push_back(&VSMapping);
break; break;
} }
case TargetOpcode::G_LOAD: { case TargetOpcode::G_LOAD:
case TargetOpcode::G_ZEXTLOAD:
case TargetOpcode::G_SEXTLOAD: {
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
LLT PtrTy = MRI.getType(MI.getOperand(1).getReg()); LLT PtrTy = MRI.getType(MI.getOperand(1).getReg());
unsigned PtrSize = PtrTy.getSizeInBits(); unsigned PtrSize = PtrTy.getSizeInBits();
unsigned AS = PtrTy.getAddressSpace(); unsigned AS = PtrTy.getAddressSpace();
LLT LoadTy = MRI.getType(MI.getOperand(0).getReg()); LLT LoadTy = MRI.getType(MI.getOperand(0).getReg());
if (isInstrUniformNonExtLoad(MI) && if (isInstrUniformNonExtLoad(MI) &&
(AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS)) { (AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS)) {
const InstructionMapping &SSMapping = getInstructionMapping( const InstructionMapping &SSMapping = getInstructionMapping(
▲ Show 20 Lines • Show All 929 Lines • ▼ Show 20 Lines case Intrinsic::amdgcn_s_sendmsghalt: {
constrainOpWithReadfirstlane(MI, MRI, 2); // M0 constrainOpWithReadfirstlane(MI, MRI, 2); // M0
return; return;
} }
default: default:
break; break;
} }
break; break;
} }
case AMDGPU::G_LOAD: { case AMDGPU::G_LOAD:
case AMDGPU::G_ZEXTLOAD:
case AMDGPU::G_SEXTLOAD: {
if (applyMappingWideLoad(MI, OpdMapper, MRI)) if (applyMappingWideLoad(MI, OpdMapper, MRI))
return; return;
break; break;
} }
default: default:
break; break;
} }
▲ Show 20 Lines • Show All 853 Lines • ▼ Show 20 Lines if (Size == 64) {
OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size); OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size); OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size);
} }
break; break;
} }
case AMDGPU::G_LOAD: case AMDGPU::G_LOAD:
case AMDGPU::G_ZEXTLOAD:
case AMDGPU::G_SEXTLOAD:
return getInstrMappingForLoad(MI); return getInstrMappingForLoad(MI);
case AMDGPU::G_ATOMICRMW_XCHG: case AMDGPU::G_ATOMICRMW_XCHG:
case AMDGPU::G_ATOMICRMW_ADD: case AMDGPU::G_ATOMICRMW_ADD:
case AMDGPU::G_ATOMICRMW_SUB: case AMDGPU::G_ATOMICRMW_SUB:
case AMDGPU::G_ATOMICRMW_AND: case AMDGPU::G_ATOMICRMW_AND:
case AMDGPU::G_ATOMICRMW_OR: case AMDGPU::G_ATOMICRMW_OR:
case AMDGPU::G_ATOMICRMW_XOR: case AMDGPU::G_ATOMICRMW_XOR:
Show All 25 Lines

test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: sextload_constant_i8_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: sextload_constant_i8_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 4)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 4, align 1)
...
---
name: sextload_global_i8_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: sextload_global_i8_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 1)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1, align 1)
...
---
name: sextload_constant_i16_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: sextload_constant_i16_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 4)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 4, align 2)
...
---
name: sextload_global_i16_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: sextload_global_i16_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 1)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 1, align 2)
...
---
name: sextload_local_i8_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: sextload_local_i8_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p3) :: (load 1, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 3, align 1)
...
---
name: sextload_local_i16_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: sextload_local_i16_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p3) :: (load 2, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 3, align 2)
...
!

test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: zextload_constant_i8_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: zextload_constant_i8_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 4)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 4, align 1)
...
---
name: zextload_global_i8_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: zextload_global_i8_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 1, addrspace 1)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1, align 1)
...
---
name: zextload_constant_i16_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: zextload_constant_i16_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 4)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 4, align 2)
...
---
name: zextload_global_i16_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: zextload_global_i16_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p4) :: (load 2, addrspace 1)
%0:_(p4) = COPY $sgpr0_sgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 1, align 2)
...
---
name: zextload_local_i8_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: zextload_local_i8_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p3) :: (load 1, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 3, align 1)
...
---
name: zextload_local_i16_to_i32_uniform
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: zextload_local_i16_to_i32_uniform
; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
; CHECK: [[ZEXTLOAD:%[0-9]+]]:vgpr(s32) = G_ZEXTLOAD [[COPY1]](p3) :: (load 2, addrspace 3)
%0:_(p3) = COPY $sgpr0
%1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 3, align 2)
...