This is an archive of the discontinued LLVM Phabricator instance.

Differential D66929

[MIPS GlobalISel] Lower fptoui
ClosedPublic

Authored by Petar.Avramovic on Aug 29 2019, 1:00 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG6412b56513a3: [MIPS GlobalISel] Lower fptoui
rL370431: [MIPS GlobalISel] Lower fptoui
Summary

Add lower for G_FPTOUI. Algorithm is similar to the SDAG version
in TargetLowering::expandFP_TO_UINT.
Lower G_FPTOUI for MIPS32.

Diff Detail

Event Timeline

Petar.Avramovic created this revision.Aug 29 2019, 1:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 29 2019, 1:00 AM
Herald added subscribers: llvm-commits, volkan, jrtc27 and 3 others. · View Herald Transcript
atanasyan accepted this revision.Aug 29 2019, 6:53 AM

LGTM

This revision is now accepted and ready to land.Aug 29 2019, 6:53 AM
Closed by commit rL370431: [MIPS GlobalISel] Lower fptoui (authored by Petar.Avramovic). · Explain WhyAug 29 2019, 10:47 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
include/
llvm/
CodeGen/
GlobalISel/
1 line
lib/
CodeGen/
GlobalISel/
44 lines
Target/
Mips/
1 line
test/
CodeGen/
Mips/
GlobalISel/
legalizer/
274 lines
llvm-ir/
216 lines

Diff 217790

include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 Linespublic:
LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty); LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty); LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty); LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI); LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI);
LegalizeResult lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty); LegalizeResult lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty); LegalizeResult lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty); LegalizeResult lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty); LegalizeResult lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI); LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
LegalizeResult lowerUnmergeValues(MachineInstr &MI); LegalizeResult lowerUnmergeValues(MachineInstr &MI);
LegalizeResult lowerShuffleVector(MachineInstr &MI); LegalizeResult lowerShuffleVector(MachineInstr &MI);
LegalizeResult lowerDynStackAlloc(MachineInstr &MI); LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
private: private:
Show All 20 Lines

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 2,119 Lines • ▼ Show 20 Lines case G_USUBE: {
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
case G_UITOFP: case G_UITOFP:
return lowerUITOFP(MI, TypeIdx, Ty); return lowerUITOFP(MI, TypeIdx, Ty);
case G_SITOFP: case G_SITOFP:
return lowerSITOFP(MI, TypeIdx, Ty); return lowerSITOFP(MI, TypeIdx, Ty);
case G_FPTOUI:
return lowerFPTOUI(MI, TypeIdx, Ty);
case G_SMIN: case G_SMIN:
case G_SMAX: case G_SMAX:
case G_UMIN: case G_UMIN:
case G_UMAX: case G_UMAX:
return lowerMinMax(MI, TypeIdx, Ty); return lowerMinMax(MI, TypeIdx, Ty);
case G_FCOPYSIGN: case G_FCOPYSIGN:
return lowerFCopySign(MI, TypeIdx, Ty); return lowerFCopySign(MI, TypeIdx, Ty);
case G_FMINNUM: case G_FMINNUM:
▲ Show 20 Lines • Show All 1,574 Lines • ▼ Show 20 Lines auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
MIRBuilder.buildConstant(S64, 0)); MIRBuilder.buildConstant(S64, 0));
MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
return Legalized; return Legalized;
} }
return UnableToLegalize; return UnableToLegalize;
} }
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
Register Dst = MI.getOperand(0).getReg();
Register Src = MI.getOperand(1).getReg();
LLT DstTy = MRI.getType(Dst);
LLT SrcTy = MRI.getType(Src);
const LLT S64 = LLT::scalar(64);
const LLT S32 = LLT::scalar(32);
if (SrcTy != S64 && SrcTy != S32)
return UnableToLegalize;
if (DstTy != S32 && DstTy != S64)
return UnableToLegalize;
// FPTOSI gives same result as FPTOUI for positive signed integers.
// FPTOUI needs to deal with fp values that convert to unsigned integers
// greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
: APFloat::IEEEdouble(),
APInt::getNullValue(SrcTy.getSizeInBits()));
TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
// For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
// (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
MachineInstrBuilder FCMP =
MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, DstTy, Src, Threshold);
MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
MI.eraseFromParent();
return Legalized;
}
static CmpInst::Predicate minMaxToCompare(unsigned Opc) { static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
switch (Opc) { switch (Opc) {
case TargetOpcode::G_SMIN: case TargetOpcode::G_SMIN:
return CmpInst::ICMP_SLT; return CmpInst::ICMP_SLT;
case TargetOpcode::G_SMAX: case TargetOpcode::G_SMAX:
return CmpInst::ICMP_SGT; return CmpInst::ICMP_SGT;
case TargetOpcode::G_UMIN: case TargetOpcode::G_UMIN:
return CmpInst::ICMP_ULT; return CmpInst::ICMP_ULT;
▲ Show 20 Lines • Show All 228 Lines • Show Last 20 Lines

lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
// FP to int conversion instructions // FP to int conversion instructions
getActionDefinitionsBuilder(G_FPTOSI) getActionDefinitionsBuilder(G_FPTOSI)
.legalForCartesianProduct({s32}, {s64, s32}) .legalForCartesianProduct({s32}, {s64, s32})
.libcallForCartesianProduct({s64}, {s64, s32}) .libcallForCartesianProduct({s64}, {s64, s32})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder(G_FPTOUI) getActionDefinitionsBuilder(G_FPTOUI)
.libcallForCartesianProduct({s64}, {s64, s32}) .libcallForCartesianProduct({s64}, {s64, s32})
.lowerForCartesianProduct({s32}, {s64, s32})
.minScalar(0, s32); .minScalar(0, s32);
// Int to FP conversion instructions // Int to FP conversion instructions
getActionDefinitionsBuilder(G_SITOFP) getActionDefinitionsBuilder(G_SITOFP)
.legalForCartesianProduct({s64, s32}, {s32}) .legalForCartesianProduct({s64, s32}, {s32})
.libcallForCartesianProduct({s64, s32}, {s64}) .libcallForCartesianProduct({s64, s32}, {s64})
.minScalar(1, s32); .minScalar(1, s32);
Show All 38 Lines

test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- | --- |
define void @f32toi64() {entry: ret void} define void @f32toi64() {entry: ret void}
define void @f32toi32() {entry: ret void} define void @f32toi32() {entry: ret void}
define void @f32toi16() {entry: ret void} define void @f32toi16() {entry: ret void}
define void @f32toi8() {entry: ret void} define void @f32toi8() {entry: ret void}
define void @f64toi64() {entry: ret void} define void @f64toi64() {entry: ret void}
define void @f64toi32() {entry: ret void} define void @f64toi32() {entry: ret void}
define void @f64toi16() {entry: ret void} define void @f64toi16() {entry: ret void}
define void @f64toi8() {entry: ret void} define void @f64toi8() {entry: ret void}
define void @f32tou64() {entry: ret void} define void @f32tou64() {entry: ret void}
define void @f32tou32() {entry: ret void}
define void @f32tou16() {entry: ret void}
define void @f32tou8() {entry: ret void}
define void @f64tou64() {entry: ret void} define void @f64tou64() {entry: ret void}
define void @f64tou32() {entry: ret void}
define void @f64tou16() {entry: ret void}
define void @f64tou8() {entry: ret void}
... ...
--- ---
name: f32toi64 name: f32toi64
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
▲ Show 20 Lines • Show All 299 Lines • ▼ Show 20 Lines bb.1.entry:
%1:_(s64) = G_FPTOUI %0(s32) %1:_(s64) = G_FPTOUI %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
$v1 = COPY %3(s32) $v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1 RetRA implicit $v0, implicit $v1
... ...
--- ---
name: f32tou32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32tou32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32: $v0 = COPY [[SELECT]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64: $v0 = COPY [[SELECT]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s32) = G_FPTOUI %0(s32)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: f32tou16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32tou16
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: $v0 = COPY [[AND]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou16
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: $v0 = COPY [[AND]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s16) = G_FPTOUI %0(s32)
%2:_(s32) = G_ZEXT %1(s16)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: f32tou8
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: f32tou8
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: $v0 = COPY [[AND]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou8
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: $v0 = COPY [[AND]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s8) = G_FPTOUI %0(s32)
%2:_(s32) = G_ZEXT %1(s8)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: f64tou64 name: f64tou64
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $d6 liveins: $d6
; FP32-LABEL: name: f64tou64 ; FP32-LABEL: name: f64tou64
Show All 23 Lines bb.1.entry:
%0:_(s64) = COPY $d6 %0:_(s64) = COPY $d6
%1:_(s64) = G_FPTOUI %0(s64) %1:_(s64) = G_FPTOUI %0(s64)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
$v1 = COPY %3(s32) $v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1 RetRA implicit $v0, implicit $v1
... ...
---
name: f64tou32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64tou32
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32: $v0 = COPY [[SELECT]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou32
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64: $v0 = COPY [[SELECT]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s32) = G_FPTOUI %0(s64)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: f64tou16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64tou16
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: $v0 = COPY [[AND]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou16
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: $v0 = COPY [[AND]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s16) = G_FPTOUI %0(s64)
%2:_(s32) = G_ZEXT %1(s16)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: f64tou8
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: f64tou8
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: $v0 = COPY [[AND]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou8
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: $v0 = COPY [[AND]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s8) = G_FPTOUI %0(s64)
%2:_(s32) = G_ZEXT %1(s8)
$v0 = COPY %2(s32)
RetRA implicit $v0
...

test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; MIPS32-NEXT: addiu $sp, $sp, 24 ; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%conv = fptoui float %a to i64 %conv = fptoui float %a to i64
ret i64 %conv ret i64 %conv
} }
define i32 @f32tou32(float %a) {
; MIPS32-LABEL: f32tou32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: lui $2, 20224
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptoui float %a to i32
ret i32 %conv
}
define zeroext i16 @f32tou16(float %a) {
; MIPS32-LABEL: f32tou16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: lui $2, 20224
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: ori $1, $zero, 65535
; MIPS32-NEXT: and $2, $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptoui float %a to i16
ret i16 %conv
}
define zeroext i8 @f32tou8(float %a) {
; MIPS32-LABEL: f32tou8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: lui $2, 20224
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: ori $1, $zero, 255
; MIPS32-NEXT: and $2, $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%conv = fptoui float %a to i8
ret i8 %conv
}
define i64 @f64tou64(double %a) { define i64 @f64tou64(double %a) {
; MIPS32-LABEL: f64tou64: ; MIPS32-LABEL: f64tou64:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24 ; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill ; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4 ; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal __fixunsdfdi ; MIPS32-NEXT: jal __fixunsdfdi
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24 ; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%conv = fptoui double %a to i64 %conv = fptoui double %a to i64
ret i64 %conv ret i64 %conv
} }
define i32 @f64tou32(double %a) {
; FP32-LABEL: f64tou32:
; FP32: # %bb.0: # %entry
; FP32-NEXT: trunc.w.d $f0, $f12
; FP32-NEXT: mfc1 $1, $f0
; FP32-NEXT: lui $2, 16864
; FP32-NEXT: ori $3, $zero, 0
; FP32-NEXT: mtc1 $3, $f2
; FP32-NEXT: mtc1 $2, $f3
; FP32-NEXT: sub.d $f4, $f12, $f2
; FP32-NEXT: trunc.w.d $f0, $f4
; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f2
; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: f64tou32:
; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f1
; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: sub.d $f2, $f12, $f1
; FP64-NEXT: trunc.w.d $f0, $f2
; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f1
; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:
%conv = fptoui double %a to i32
ret i32 %conv
}
define zeroext i16 @f64tou16(double %a) {
; FP32-LABEL: f64tou16:
; FP32: # %bb.0: # %entry
; FP32-NEXT: trunc.w.d $f0, $f12
; FP32-NEXT: mfc1 $1, $f0
; FP32-NEXT: lui $2, 16864
; FP32-NEXT: ori $3, $zero, 0
; FP32-NEXT: mtc1 $3, $f2
; FP32-NEXT: mtc1 $2, $f3
; FP32-NEXT: sub.d $f4, $f12, $f2
; FP32-NEXT: trunc.w.d $f0, $f4
; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f2
; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: ori $1, $zero, 65535
; FP32-NEXT: and $2, $2, $1
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: f64tou16:
; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f1
; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: sub.d $f2, $f12, $f1
; FP64-NEXT: trunc.w.d $f0, $f2
; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f1
; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: ori $1, $zero, 65535
; FP64-NEXT: and $2, $2, $1
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:
%conv = fptoui double %a to i16
ret i16 %conv
}
define zeroext i8 @f64tou8(double %a) {
; FP32-LABEL: f64tou8:
; FP32: # %bb.0: # %entry
; FP32-NEXT: trunc.w.d $f0, $f12
; FP32-NEXT: mfc1 $1, $f0
; FP32-NEXT: lui $2, 16864
; FP32-NEXT: ori $3, $zero, 0
; FP32-NEXT: mtc1 $3, $f2
; FP32-NEXT: mtc1 $2, $f3
; FP32-NEXT: sub.d $f4, $f12, $f2
; FP32-NEXT: trunc.w.d $f0, $f4
; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f2
; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: ori $1, $zero, 255
; FP32-NEXT: and $2, $2, $1
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: f64tou8:
; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f1
; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: sub.d $f2, $f12, $f1
; FP64-NEXT: trunc.w.d $f0, $f2
; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f1
; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: ori $1, $zero, 255
; FP64-NEXT: and $2, $2, $1
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:
%conv = fptoui double %a to i8
ret i8 %conv
}