[RISCV] Implement RISCVRegisterInfo::getPointerRegClass

[luismarques]

Summary

TargetRegisterInfo::getPointerRegClass is used, directly and indirectly, by several passes and CodeGen so it should be implemented (overridden) for RISC-V too.

@reshabh This will probably affect your GSoC work implementing 64-bit pointers on RV32. Not sure what the status of that is and how you want to proceed, but I imagine you'll just tweak this method once this patch is committed?

[lenary]

LGTM with one question:

This should be causing an assert everywhere it's used right now, shouldn't it? I'm confused that we're not seeing any of those asserts/failures in our testcases.

[luismarques]

In D66752#1646711, @lenary wrote:

This should be causing an assert everywhere it's used right now, shouldn't it? I'm confused that we're not seeing any of those asserts/failures in our testcases.

That's because overall it's not used much, so we were "lucky" not to hit the assert. But your reasoning makes sense.

[lenary]

In D66752#1646805, @luismarques wrote:

In D66752#1646711, @lenary wrote:

This should be causing an assert everywhere it's used right now, shouldn't it? I'm confused that we're not seeing any of those asserts/failures in our testcases.

That's because overall it's not used much, so we were "lucky" not to hit the assert. But your reasoning makes sense.

Ok, cool. I'm happy for this to land without a testcase.

[asb]

This triggers when building the Linux kernel too. I forgot to submit this patch after getting that working. I also couldn't get a meaningful test case for it that didn't seem like it would be horribly brittle. LGTM, thanks.

[luismarques]

In D66752#1646844, @lenary wrote:

Ok, cool. I'm happy for this to land without a testcase.

I didn’t add a test case because it would be too fragile and would only test that method very indirectly.

[reshabh]

Thanks for letting me know about this, right now we are focusing on getting some perf numbers out of it. After testing I'll merge all latest commits from the upstream then I think it will be totally viable to tweak this method for 64 bit pointer support. Again thanks for keeping me in the loop.

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
 
   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
   bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
     return true;
   }
+
+  const TargetRegisterClass *
+  getPointerRegClass(const MachineFunction &MF,
+                     unsigned Kind = 0) const override {
+    return &RISCV::GPRRegClass;
+  }
 };
 }
 
 #endif