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Differential D66205

[MIPS GlobalISel] NarrowScalar G_ZEXTLOAD and G_SEXTLOAD
ClosedPublic

Authored by Petar.Avramovic on Aug 14 2019, 1:56 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG7f581df64901: [MIPS GlobalISel] NarrowScalar G_ZEXTLOAD and G_SEXTLOAD
rL369512: [MIPS GlobalISel] NarrowScalar G_ZEXTLOAD and G_SEXTLOAD
Summary

NarrowScalar G_ZEXTLOAD and G_SEXTLOAD to s32 for MIPS32.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Aug 14 2019, 1:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 14 2019, 1:56 AM
Herald added subscribers: llvm-commits, jrtc27, arichardson and 2 others. · View Herald Transcript
Petar.Avramovic added a parent revision: D66204: [MIPS GlobalISel] NarrowScalar G_ZEXT and G_SEXT.Aug 14 2019, 1:57 AM
atanasyan accepted this revision.Aug 14 2019, 9:21 AM

LGTM

This revision is now accepted and ready to land.Aug 14 2019, 9:21 AM
Closed by commit rL369512: [MIPS GlobalISel] NarrowScalar G_ZEXTLOAD and G_SEXTLOAD (authored by Petar.Avramovic). · Explain WhyAug 21 2019, 2:42 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
6 lines
test/
CodeGen/
Mips/
GlobalISel/
legalizer/
57 lines
llvm-ir/
28 lines
mips-prelegalizer-combiner/
52 lines
regbankselect/
63 lines

Diff 216357

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder(G_UNMERGE_VALUES) getActionDefinitionsBuilder(G_UNMERGE_VALUES)
.legalFor({{s32, s64}}); .legalFor({{s32, s64}});
getActionDefinitionsBuilder(G_MERGE_VALUES) getActionDefinitionsBuilder(G_MERGE_VALUES)
.legalFor({{s64, s32}}); .legalFor({{s64, s32}});
getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD}) getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
.legalForTypesWithMemDesc({{s32, p0, 8, 8}, .legalForTypesWithMemDesc({{s32, p0, 8, 8},
{s32, p0, 16, 8}}) {s32, p0, 16, 8}})
.minScalar(0, s32); .clampScalar(0, s32, s32);
getActionDefinitionsBuilder({G_ZEXT, G_SEXT}) getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
.legalIf([](const LegalityQuery &Query) { return false; }) .legalIf([](const LegalityQuery &Query) { return false; })
.maxScalar(0, s32); .maxScalar(0, s32);
getActionDefinitionsBuilder(G_TRUNC) getActionDefinitionsBuilder(G_TRUNC)
.legalIf([](const LegalityQuery &Query) { return false; }) .legalIf([](const LegalityQuery &Query) { return false; })
.maxScalar(1, s32); .maxScalar(1, s32);
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- | --- |
define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void} define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void} define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void} define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void} define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
... ...
--- ---
name: load1_s8_to_zextLoad1_s32 name: load1_s8_to_zextLoad1_s32
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0 %0:_(p0) = COPY $a0
%3:_(s32) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.px) %3:_(s32) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.px)
$v0 = COPY %3(s32) $v0 = COPY %3(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: load4_s32_to_zextLoad4_s64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[C]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load1_s8_to_sextLoad1_s32 name: load1_s8_to_sextLoad1_s32
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0 %0:_(p0) = COPY $a0
%3:_(s32) = G_SEXTLOAD %0(p0) :: (load 1 from %ir.px) %3:_(s32) = G_SEXTLOAD %0(p0) :: (load 1 from %ir.px)
$v0 = COPY %3(s32) $v0 = COPY %3(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
---
name: load4_s32_to_sextLoad4_s64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[ASHR]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load 4 from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%0 = load i8, i8* %px %0 = load i8, i8* %px
%conv = zext i8 %0 to i16 %conv = zext i8 %0 to i16
ret i16 %conv ret i16 %conv
} }
define i64 @load4_s32_to_zextLoad4_s64(i32* %px) {
; MIPS32-LABEL: load4_s32_to_zextLoad4_s64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%0 = load i32, i32* %px
%conv = zext i32 %0 to i64
ret i64 %conv
}
define i32 @load1_s8_to_sextLoad1_s32(i8* %px) { define i32 @load1_s8_to_sextLoad1_s32(i8* %px) {
; MIPS32-LABEL: load1_s8_to_sextLoad1_s32: ; MIPS32-LABEL: load1_s8_to_sextLoad1_s32:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lb $2, 0($4) ; MIPS32-NEXT: lb $2, 0($4)
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%0 = load i8, i8* %px %0 = load i8, i8* %px
Show All 31 Lines
; MIPS32-NEXT: lb $2, 0($4) ; MIPS32-NEXT: lb $2, 0($4)
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%0 = load i8, i8* %px %0 = load i8, i8* %px
%conv = sext i8 %0 to i16 %conv = sext i8 %0 to i16
ret i16 %conv ret i16 %conv
} }
define i64 @load4_s32_to_sextLoad4_s64(i32* %px) {
; MIPS32-LABEL: load4_s32_to_sextLoad4_s64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $1, 0($4)
; MIPS32-NEXT: ori $2, $zero, 31
; MIPS32-NEXT: srav $3, $1, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%0 = load i32, i32* %px
%conv = sext i32 %0 to i64
ret i64 %conv
}

llvm/trunk/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- | --- |
define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void} define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void} define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void} define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void} define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
... ...
--- ---
name: load1_s8_to_zextLoad1_s32 name: load1_s8_to_zextLoad1_s32
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines bb.1.entry:
%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px) %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
%2:_(s16) = G_ZEXT %1(s8) %2:_(s16) = G_ZEXT %1(s8)
%3:_(s32) = G_ZEXT %2(s16) %3:_(s32) = G_ZEXT %2(s16)
$v0 = COPY %3(s32) $v0 = COPY %3(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: load4_s32_to_zextLoad4_s64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXTLOAD]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
%2:_(s64) = G_ZEXT %1(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load1_s8_to_sextLoad1_s32 name: load1_s8_to_sextLoad1_s32
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32 ; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines bb.1.entry:
%0:_(p0) = COPY $a0 %0:_(p0) = COPY $a0
%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px) %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
%2:_(s16) = G_SEXT %1(s8) %2:_(s16) = G_SEXT %1(s8)
%3:_(s32) = G_SEXT %2(s16) %3:_(s32) = G_SEXT %2(s16)
$v0 = COPY %3(s32) $v0 = COPY %3(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
---
name: load4_s32_to_sextLoad4_s64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXTLOAD]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
%2:_(s64) = G_SEXT %1(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- | --- |
define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void} define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void} define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void} define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
... ...
--- ---
name: load1_s8_to_zextLoad1_s32 name: load1_s8_to_zextLoad1_s32
alignment: 2 alignment: 2
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
Show All 29 Lines bb.1.entry:
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0 %0:_(p0) = COPY $a0
%2:_(s32) = G_ZEXTLOAD %0(p0) :: (load 2 from %ir.px) %2:_(s32) = G_ZEXTLOAD %0(p0) :: (load 2 from %ir.px)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
--- ---
name: load4_s32_to_zextLoad4_s64
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: $v1 = COPY [[C]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
%6:_(s32) = G_CONSTANT i32 0
%2:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load1_s8_to_sextLoad1_s32 name: load1_s8_to_sextLoad1_s32
alignment: 2 alignment: 2
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
Show All 25 Lines bb.1.entry:
; MIPS32: $v0 = COPY [[SEXTLOAD]](s32) ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0 ; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0 %0:_(p0) = COPY $a0
%2:_(s32) = G_SEXTLOAD %0(p0) :: (load 2 from %ir.px) %2:_(s32) = G_SEXTLOAD %0(p0) :: (load 2 from %ir.px)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
---
name: load4_s32_to_sextLoad4_s64
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[LOAD]], [[COPY1]](s32)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: $v1 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%5:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
%9:_(s32) = G_CONSTANT i32 31
%10:_(s32) = G_CONSTANT i32 0
%8:_(s32) = COPY %9(s32)
%7:_(s32) = G_ASHR %5, %8(s32)
%2:_(s64) = G_MERGE_VALUES %5(s32), %7(s32)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...