[AArch64][GlobalISel] RBS: Treat s128s like vectors when unmerging

[aemerson]

Summary

The destinations should be FPRs (for now).

[paquette]

LGTM

llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

case TargetOpcode::G_UNMERGE_VALUES: {
     // If the first operand belongs to a FPR register bank, then make sure that
     // we preserve that.
     if (OpRegBankIdx[0] != PMI_FirstGPR)
       break;
 
     LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
     // UNMERGE into scalars from a vector should always use FPR.
     // Likewise if any of the uses are FP instructions.
-    if (SrcTy.isVector() ||
+    if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
         any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
                [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {
       // Set the register bank of every operand to FPR.
       for (unsigned Idx = 0, NumOperands = MI.getNumOperands();
            Idx < NumOperands; ++Idx)
         OpRegBankIdx[Idx] = PMI_FirstFPR;
     }
     break;

llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir

bb.0:
     ; CHECK: $x0 = COPY [[UV]](s64)
     ; CHECK: RET_ReallyLR implicit $x0
     %0:_(<2 x s64>) = COPY $q0
     %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(<2 x s64>)
     $x0 = COPY %1(s64)
     RET_ReallyLR implicit $x0
 
 ...
+---
+name:            unmerge_s128
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+frameInfo:
+  maxCallFrameSize: 0
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; s128 should be treated as an FPR/vector because it can't live on GPR bank.
+    ; CHECK-LABEL: name: unmerge_s128
+    ; CHECK: liveins: $q0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s128) = COPY $q0
+    ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+    ; CHECK: $x0 = COPY [[UV]](s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %0:_(s128) = COPY $q0
+    %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(s128)
+    $x0 = COPY %1(s64)
+    RET_ReallyLR implicit $x0
+
+...