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Differential D66166

[WebAssembly] Stop unrolling SIMD shifts since they are fixed in V8
ClosedPublic

Authored by tlively on Aug 13 2019, 2:06 PM.

Details

Reviewers
aheejin
Commits
rGde0133eaa2c5: [WebAssembly] Stop unrolling SIMD shifts since they are fixed in V8
rL368868: [WebAssembly] Stop unrolling SIMD shifts since they are fixed in V8
Summary

Fixes PR42973. Tests don't change because simd-arith.ll tests behavior
on unimplemented-simd128, which does not include any temporary
workarounds such as the one removed in this revision.

Diff Detail

Repository
rL LLVM

Event Timeline

tlively created this revision.Aug 13 2019, 2:06 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 13 2019, 2:06 PM
Herald added subscribers: llvm-commits, dmgreen, sunfish and 4 others. · View Herald Transcript
Harbormaster completed remote builds in B36692: Diff 214914.Aug 13 2019, 2:06 PM
aheejin accepted this revision.Aug 14 2019, 1:03 AM
This revision is now accepted and ready to land.Aug 14 2019, 1:03 AM
aheejin mentioned this in D66218: [WebAssembly] Lower SIMD shifts since they are fixed in V8.Aug 14 2019, 8:17 AM
Closed by commit rL368868: [WebAssembly] Stop unrolling SIMD shifts since they are fixed in V8 (authored by tlively). · Explain WhyAug 14 2019, 9:24 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
WebAssembly/
5 lines

Diff 215140

llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

Show First 20 Lines • Show All 1,443 Lines • ▼ Show 20 Lines
SDValue WebAssemblyTargetLowering::LowerShift(SDValue Op, SDValue WebAssemblyTargetLowering::LowerShift(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
// Only manually lower vector shifts // Only manually lower vector shifts
assert(Op.getSimpleValueType().isVector()); assert(Op.getSimpleValueType().isVector());
// Expand all vector shifts until V8 fixes its implementation
// TODO: remove this once V8 is fixed
if (!Subtarget->hasUnimplementedSIMD128())
return unrollVectorShift(Op, DAG);
// Unroll non-splat vector shifts // Unroll non-splat vector shifts
BuildVectorSDNode *ShiftVec; BuildVectorSDNode *ShiftVec;
SDValue SplatVal; SDValue SplatVal;
if (!(ShiftVec = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) || if (!(ShiftVec = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) ||
!(SplatVal = ShiftVec->getSplatValue())) !(SplatVal = ShiftVec->getSplatValue()))
return unrollVectorShift(Op, DAG); return unrollVectorShift(Op, DAG);
// All splats except i64x2 const splats are handled by patterns // All splats except i64x2 const splats are handled by patterns
Show All 27 Lines