SROA: Check Total Bits of vector type

[ssarda]

Summary

SROA: Check Total Bits of vector type

While Promoting alloca instruction of Vector Type, Check total size in bits of its slices too.
If they don't match, don't promote the alloca instruction.

Bug : https://bugs.llvm.org/show_bug.cgi?id=42585

[arsenm]

llvm/test/Transforms/SROA/vector-promotion-different-size.ll

14

Can you add some more tests with mismatched element types?

[ssarda]

Updated with 1 more test case.

[ssarda]

llvm/test/Transforms/SROA/vector-promotion-different-size.ll

14

Added one more case

[ssarda]

Gentle Ping!!

[ssarda]

@arsenm
@t.p.northover
@reames

Gentle Ping !! I would be grateful if someone can review the updated patch.

[arsenm]

This seems reasonable

llvm/lib/Transforms/Scalar/SROA.cpp

1892–1896

Can you add a comment that this is for bitcats to vectors with different numbers of elements?

[ssarda]

Added comment as suggested.

[ssarda]

Committed in https://llvm.org/viewvc/llvm-project?view=revision&revision=372480

I better take care to mention phab link of approval in commit message next time.

llvm/lib/Transforms/Scalar/SROA.cpp

 static VectorType *isVectorPromotionViable(Partition &P, const DataLayout &DL) {
   // Collect the candidate types for vector-based promotion. Also track whether
   // we have different element types.
   SmallVector<VectorType *, 4> CandidateTys;
   Type *CommonEltTy = nullptr;
   bool HaveCommonEltTy = true;
   auto CheckCandidateType = [&](Type *Ty) {
     if (auto *VTy = dyn_cast<VectorType>(Ty)) {
+      if (!CandidateTys.empty()) {
+        VectorType *V = CandidateTys[0];
+        if (DL.getTypeSizeInBits(VTy) != DL.getTypeSizeInBits(V)) {
+          CandidateTys.clear();
+          return;
+        }
+      }
       CandidateTys.push_back(VTy);
       if (!CommonEltTy)
         CommonEltTy = VTy->getElementType();
       else if (CommonEltTy != VTy->getElementType())
         HaveCommonEltTy = false;
     }
   };
   // Consider any loads or stores that are the exact size of the slice.

llvm/test/Transforms/SROA/vector-promotion-different-size.ll

+; RUN: opt < %s -sroa -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
+
+define <4 x i1> @vector_bitcast() {
+  ; CHECK-LABEL: @vector_bitcast
+  ; CHECK: alloca i1
+
+    %a = alloca <3 x i1>
+    store <3 x i1> <i1 1,i1 0,i1 1>, <3 x i1>* %a
+    %cast = bitcast <3 x i1>* %a to <4 x i1>*
+    %vec = load <4 x i1>, <4 x i1>* %cast
+    ret <4 x i1> %vec
+}
+
+define void @vector_bitcast_2() {
+  ; CHECK-LABEL: @vector_bitcast_2
+  ; CHECK: alloca <32 x i16>
+
+    %"sum$1.host2" = alloca <32 x i16>
+    store <32 x i16> undef, <32 x i16>* %"sum$1.host2"
+    %bc = bitcast <32 x i16>* %"sum$1.host2" to <64 x i16>*
+    %bcl = load <64 x i16>, <64 x i16>* %bc
+    ret void
+}