In D136051#3931086, @bcahoon wrote:

Hi @ssarda, thanks for the test case. That helps to understand the problem. Which appears to be the following MIR,

INLINEASM &"$0 = insert($1,#31,#1);" [attdialect], $0:[regdef], implicit-def $r7, $1:[reguse:IntRegs], %45:intregs
%32:intregs = COPY $r7
$r7 = COPY %32:intregs

These instructions are scheduled in the same cycle. Then, isValidSchedule rejects this because :

// Furthermore, if a physical def/use pair is assigned to the same
// cycle, orderDependence does not guarantee def/use ordering, so that
// case should be considered invalid.

@bcahoon attached a test case

This patch is causing issue mentioned in https://discourse.llvm.org/t/sema-section-type-conflict/66000

Hi @bcahoon, i am yet to come across a case in Hexagon where in a linear list of instruction, a use occurs before def in orderDependence(). I assume, that's never a case for Hexagon happening yet. As pointed out by @dpenry, orderDependence() is not robust for other targets to make sure that def-use are in proper order, because of which we are trying to avoid same cycle scheduling by having check in isValidSchedule() function. But since, this is not the case with Hexagon target, this patch enables same cycle def-use scheduling for only Hexagon with a flag. Let us know your thoughts over it.

I agree that orderDependence() need to be more robust. However, we can't penalize pipeliner scheduling where def-use are in same cycle. I may add a TODO as of now and keep the flag. Once orderDependence() is fixed, we may remove the flag. Does it sound good?

Committed in https://llvm.org/viewvc/llvm-project?view=revision&revision=372480

Added comment as suggested.

Gentle Ping !! I would be grateful if someone can review the updated patch.

Gentle Ping!!

Updated with 1 more test case.