[AArch64] Do not allocate unnecessary emergency slot.

[sdesmalen]

Summary

Fix an issue where the compiler still allocates an emergency spill slot even
though it already decided to spill an extra callee-save register to use
as a scratch register.

[thegameg]

This LGTM, thanks!

test/CodeGen/AArch64/extra-callee-save.mir

7 ↗

(On Diff #212542)

You should be able to get rid of the IR completely here.

llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp

void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
   // The frame record needs to be created by saving the appropriate registers
   unsigned EstimatedStackSize = MFI.estimateStackSize(MF);
   if (hasFP(MF) ||
       windowsRequiresStackProbe(MF, EstimatedStackSize + CSStackSize + 16)) {
     SavedRegs.set(AArch64::FP);
     SavedRegs.set(AArch64::LR);
   }
 
-  LLVM_DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:";
+  LLVM_DEBUG(dbgs() << "*** determineCalleeSaves\nSaved CSRs:";
              for (unsigned Reg
                   : SavedRegs.set_bits()) dbgs()
              << ' ' << printReg(Reg, RegInfo);
              dbgs() << "\n";);
 
   // If any callee-saved registers are used, the frame cannot be eliminated.
   bool CanEliminateFrame = SavedRegs.count() == 0;
 
if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) {
       LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
                         << " to get a scratch register.\n");
       SavedRegs.set(UnspilledCSGPR);
       // MachO's compact unwind format relies on all registers being stored in
       // pairs, so if we need to spill one extra for BigStack, then we need to
       // store the pair.
       if (produceCompactUnwindFrame(MF))
         SavedRegs.set(UnspilledCSGPRPaired);
-      ExtraCSSpill = UnspilledCSGPRPaired;
+      ExtraCSSpill = UnspilledCSGPR;
     }
 
     // If we didn't find an extra callee-saved register to spill, create
     // an emergency spill slot.
     if (!ExtraCSSpill || MF.getRegInfo().isPhysRegUsed(ExtraCSSpill)) {
       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
       const TargetRegisterClass &RC = AArch64::GPR64RegClass;
       unsigned Size = TRI->getSpillSize(RC);

llvm/trunk/test/CodeGen/AArch64/extra-callee-save.mir

+#RUN: llc -mtriple=aarch64-- -run-pass prologepilog %s -o - | FileCheck %s
+# Check that we spill a scratch register, but not also an additional
+# emergency spill slot.
+---
+name: big_stack
+# CHECK-LABEL: name: big_stack
+# CHECK: frame-setup STPXi killed $x20, killed $x19
+# CHECK: $sp = frame-setup SUBXri $sp, 8, 12
+# CHECK-NOT: frame-setup SUBXri $sp, 16, 0
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: '', size: 32761, alignment: 8 }
+body: |
+  bb.0:
+    $x19 = IMPLICIT_DEF
+  ; $x20 can be used as scratch register.
+    $x21 = IMPLICIT_DEF
+    $x22 = IMPLICIT_DEF
+    $x23 = IMPLICIT_DEF
+    $x24 = IMPLICIT_DEF
+    $x25 = IMPLICIT_DEF
+    $x26 = IMPLICIT_DEF
+    $x27 = IMPLICIT_DEF
+    $x28 = IMPLICIT_DEF
+    $lr  = IMPLICIT_DEF
+    $fp  = IMPLICIT_DEF
+    RET_ReallyLR
+...