[InstCombine] Shift amount reassociation: shl-trunc-shl pattern

[lebedev.ri]

Summary

Currently reassociateShiftAmtsOfTwoSameDirectionShifts() only handles two shifts one after another.
If the shifts are shl, we still can easily perform the fold, with no extra legality checks:
https://rise4fun.com/Alive/OQbM

If we have right-shift however, we won't be able to make it any simpler than it already is.

After this the only thing missing here is constant-folding: (NewShAmt >= bitwidth(X))

• If it's a logical shift, then constant-fold to 0 (not undef)
• If it's a ashr, then a splat of original signbit

https://rise4fun.com/Alive/E1K
https://rise4fun.com/Alive/i0V

[xbolva00]

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

32 ↗

(On Diff #212120)

Is “???” something common in this codebase? I haven’t seen it yet.

Personally I think the code gives better idea what is going on than currently the comment - (Sh0Op0 (???)) is confusing for me.

What do you think?

78 ↗

(On Diff #212120)

FIXME:

[lebedev.ri]

Rebased, addressed review notes.
Ping.

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

78 ↗

(On Diff #212120)

Right.

[spatel]

llvm/lib/IR/Constants.cpp

1590–1594 ↗

(On Diff #213427)

Would we better off copying the codegen sibling API (same type implicitly returns self)?

SelectionDAG::getZExtOrTrunc()

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

39 ↗

(On Diff #213427)

That comment isn't clear to me.

"If there is truncation of the shifted value, we must 
adjust the constraints of this fold and recreate that op." ?

[lebedev.ri]

llvm/lib/IR/Constants.cpp

1590–1594 ↗

(On Diff #213427)

I'm not sure what you have in mind here, ConstantExpr::getZExt()
will (rightfully) assert if zext is unsuitable there.
ConstantExpr::getBitCast() won't, so i suppose i could just use it,
but i really don't need bitcast here, i really want either zext or nothing.

Please can you be more specific as to what you envision here?

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

39 ↗

(On Diff #213427)

How about:

If there is a truncation inbetween these two shifts,
we must make note of it, and look through it.
The truncation will impose additional legality checks
on the transform.

?

[spatel]

LGTM

llvm/lib/IR/Constants.cpp

1590–1594 ↗

(On Diff #213427)

I'm imagining that we'll eventually (or might already) want the flexibility of returning a constant of arbitrary type (wider or narrower) since that's used in codegen regularly. But that can be a follow-on if we want.

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

39 ↗

(On Diff #213427)

That works...just some minor adjustments:

If there is a truncation between the two shifts,
we must make note of it and look through it.
The truncation imposes additional constraints
on the transform.

[lebedev.ri]

Thank you for the review!

llvm/lib/IR/Constants.cpp

1590–1594 ↗

(On Diff #213427)

Actually, looking how much extra wrappers there are around e.g. getZExtOrBitCast(),
i think i'm just gonna use it here, not sure i want to add all those and i wouldn't want to leave them out.

[rnk]

This broke the Windows bot:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/9418
The failure mode doesn't manifest until the next build due to unrelated issues:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/9419

SystemZInstrInfo.cpp fails to compile with an assert. I am working on a reduction and will send it along soon.

[rnk]

The assertion and stack trace:
https://reviews.llvm.org/P8158
clang: /usr/local/google/home/rnk/llvm-project/llvm/lib/IR/Constants.cpp:1864: static llvm::Constant *llvm::ConstantExpr::get(unsigned int, llvm::Constant *, llvm::Constant *
, unsigned int, llvm::Type *): Assertion `C1->getType() == C2->getType() && "Operand types in binary constant expression should match"' failed.
#9 0x0000000003ca39ae llvm::ConstantExpr::get(unsigned int, llvm::Constant*, llvm::Constant*, unsigned int, llvm::Type*) /usr/local/google/home/rnk/llvm-project/llvm/lib/IR/
Constants.cpp:1896:5
#10 0x00000000036e4fec llvm::ConstantFoldBinaryOpOperands(unsigned int, llvm::Constant*, llvm::Constant*, llvm::DataLayout const&) /usr/local/google/home/rnk/llvm-project/llv
m/lib/Analysis/ConstantFolding.cpp:1286:10

[lebedev.ri]

In D65380#1617668, @rnk wrote:

The assertion and stack trace:
https://reviews.llvm.org/P8158
clang: /usr/local/google/home/rnk/llvm-project/llvm/lib/IR/Constants.cpp:1864: static llvm::Constant *llvm::ConstantExpr::get(unsigned int, llvm::Constant *, llvm::Constant *
, unsigned int, llvm::Type *): Assertion `C1->getType() == C2->getType() && "Operand types in binary constant expression should match"' failed.
#9 0x0000000003ca39ae llvm::ConstantExpr::get(unsigned int, llvm::Constant*, llvm::Constant*, unsigned int, llvm::Type*) /usr/local/google/home/rnk/llvm-project/llvm/lib/IR/
Constants.cpp:1896:5
#10 0x00000000036e4fec llvm::ConstantFoldBinaryOpOperands(unsigned int, llvm::Constant*, llvm::Constant*, llvm::DataLayout const&) /usr/local/google/home/rnk/llvm-project/llv
m/lib/Analysis/ConstantFolding.cpp:1286:10

Sorry for that and thanks for the revert.

llvm/trunk/include/llvm/IR/PatternMatch.h

 
 /// Matches ZExt.
 template <typename OpTy>
 inline CastClass_match<OpTy, Instruction::ZExt> m_ZExt(const OpTy &Op) {
   return CastClass_match<OpTy, Instruction::ZExt>(Op);
 }
 
 template <typename OpTy>
+inline match_combine_or<CastClass_match<OpTy, Instruction::ZExt>, OpTy>
+m_ZExtOrSelf(const OpTy &Op) {
+  return m_CombineOr(m_ZExt(Op), Op);
+}
+
+template <typename OpTy>
 inline match_combine_or<CastClass_match<OpTy, Instruction::ZExt>,
                         CastClass_match<OpTy, Instruction::SExt>>
 m_ZExtOrSExt(const OpTy &Op) {
   return m_CombineOr(m_ZExt(Op), m_SExt(Op));
 }
 
 /// Matches UIToFP.
 template <typename OpTy>

llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp

 
 // Given pattern:
 //   (x shiftopcode Q) shiftopcode K
 // we should rewrite it as
 //   x shiftopcode (Q+K)  iff (Q+K) u< bitwidth(x)
 // This is valid for any shift, but they must be identical.
 static Instruction *
 reassociateShiftAmtsOfTwoSameDirectionShifts(BinaryOperator *Sh0,
-                                             const SimplifyQuery &SQ) {
-  // Look for:  (x shiftopcode ShAmt0) shiftopcode ShAmt1
-  Value *X, *ShAmt1, *ShAmt0;
+                                             const SimplifyQuery &SQ,
+                                             InstCombiner::BuilderTy &Builder) {
+  // Look for a shift of some instruction, ignore zext of shift amount if any.
+  Instruction *Sh0Op0;
+  Value *ShAmt0;
+  if (!match(Sh0,
+             m_Shift(m_Instruction(Sh0Op0), m_ZExtOrSelf(m_Value(ShAmt0)))))
+    return nullptr;
+
+  // If there is a truncation between the two shifts, we must make note of it
+  // and look through it. The truncation imposes additional constraints on the
+  // transform.
   Instruction *Sh1;
-  if (!match(Sh0, m_Shift(m_CombineAnd(m_Shift(m_Value(X), m_Value(ShAmt1)),
-                                       m_Instruction(Sh1)),
-                          m_Value(ShAmt0))))
+  Value *Trunc = nullptr;
+  match(Sh0Op0,
+        m_CombineOr(m_CombineAnd(m_Trunc(m_Instruction(Sh1)), m_Value(Trunc)),
+                    m_Instruction(Sh1)));
+
+  // Inner shift: (x shiftopcode ShAmt1)
+  Value *X, *ShAmt1;
+  if (!match(Sh1, m_Shift(m_Value(X), m_ZExtOrSelf(m_Value(ShAmt1)))))
     return nullptr;
 
   // The shift opcodes must be identical.
   Instruction::BinaryOps ShiftOpcode = Sh0->getOpcode();
   if (ShiftOpcode != Sh1->getOpcode())
     return nullptr;
+
+  // Did we match a pattern with truncation ?
+  if (Trunc) {
+    // For right-shifts we can't do any such simplifications. Leave as-is.
+    if (ShiftOpcode != Instruction::BinaryOps::Shl)
+      return nullptr; // FIXME: still could perform constant-folding.
+    // If we saw truncation, we'll need to produce extra instruction,
+    // and for that one of the operands of the shift must be one-use.
+    if (!match(Sh0, m_c_BinOp(m_OneUse(m_Value()), m_Value())))
+      return nullptr;
+  }
+
   // Can we fold (ShAmt0+ShAmt1) ?
-  Value *NewShAmt = SimplifyBinOp(Instruction::BinaryOps::Add, ShAmt0, ShAmt1,
-                                  SQ.getWithInstruction(Sh0));
+  auto *NewShAmt = dyn_cast_or_null<Constant>(
+      SimplifyAddInst(ShAmt0, ShAmt1, /*isNSW=*/false, /*isNUW=*/false,
+                      SQ.getWithInstruction(Sh0)));
   if (!NewShAmt)
     return nullptr; // Did not simplify.
-  // Is the new shift amount smaller than the bit width?
-  // FIXME: could also rely on ConstantRange.
-  unsigned BitWidth = X->getType()->getScalarSizeInBits();
-  if (!match(NewShAmt, m_SpecificInt_ICMP(ICmpInst::Predicate::ICMP_ULT,
-                                          APInt(BitWidth, BitWidth))))
-    return nullptr;
+  // Is the new shift amount smaller than the bit width of inner shift?
+  if (!match(NewShAmt, m_SpecificInt_ICMP(
+                           ICmpInst::Predicate::ICMP_ULT,
+                           APInt(NewShAmt->getType()->getScalarSizeInBits(),
+                                 X->getType()->getScalarSizeInBits()))))
+    return nullptr; // FIXME: could perform constant-folding.
+
   // All good, we can do this fold.
+  NewShAmt = ConstantExpr::getZExtOrBitCast(NewShAmt, X->getType());
+
   BinaryOperator *NewShift = BinaryOperator::Create(ShiftOpcode, X, NewShAmt);
-  // If both of the original shifts had the same flag set, preserve the flag.
+
+  // The flags can only be propagated if there wasn't a trunc.
+  if (!Trunc) {
+    // If the pattern did not involve trunc, and both of the original shifts
+    // had the same flag set, preserve the flag.
     if (ShiftOpcode == Instruction::BinaryOps::Shl) {
       NewShift->setHasNoUnsignedWrap(Sh0->hasNoUnsignedWrap() &&
                                      Sh1->hasNoUnsignedWrap());
       NewShift->setHasNoSignedWrap(Sh0->hasNoSignedWrap() &&
                                    Sh1->hasNoSignedWrap());
     } else {
       NewShift->setIsExact(Sh0->isExact() && Sh1->isExact());
     }
-  return NewShift;
+  }
+
+  Instruction *Ret = NewShift;
+  if (Trunc) {
+    Builder.Insert(NewShift);
+    Ret = CastInst::Create(Instruction::Trunc, NewShift, Sh0->getType());
+  }
+
+  return Ret;
 }
 
 // If we have some pattern that leaves only some low bits set, and then performs
 // left-shift of those bits, if none of the bits that are left after the final
 // shift are modified by the mask, we can omit the mask.
 //
 // There are many variants to this pattern:
 //   a)  (x & ((1 << MaskShAmt) - 1)) << ShiftShAmt
if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
       if (Instruction *R = FoldOpIntoSelect(I, SI))
         return R;
 
   if (Constant *CUI = dyn_cast<Constant>(Op1))
     if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I))
       return Res;
 
   if (Instruction *NewShift =
-          reassociateShiftAmtsOfTwoSameDirectionShifts(&I, SQ))
+          reassociateShiftAmtsOfTwoSameDirectionShifts(&I, SQ, Builder))
     return NewShift;
 
   // (C1 shift (A add C2)) -> (C1 shift C2) shift A)
   // iff A and C2 are both positive.
   Value *A;
   Constant *C;
   if (match(Op0, m_Constant()) && match(Op1, m_Add(m_Value(A), m_Constant(C))))
     if (isKnownNonNegative(A, DL, 0, &AC, &I, &DT) &&

llvm/trunk/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-shl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -instcombine -S | FileCheck %s
 
 ; Given pattern:
 ;   (trunc (x << Q) to iDst) << K
 ; we should rewrite it as
 ;   (trunc (x << (Q+K)) to iDst)  iff (Q+K) u< iDst
 ; This is only valid for shl.
 ; THIS FOLD DOES *NOT* REQUIRE ANY 'nuw'/`nsw` FLAGS!
 
 ; Basic scalar test
 
 define i16 @t0(i32 %x, i16 %y) {
 ; CHECK-LABEL: @t0(
-; CHECK-NEXT:    [[T0:%.*]] = sub i16 32, [[Y:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = zext i16 [[T0]] to i32
-; CHECK-NEXT:    [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
-; CHECK-NEXT:    [[T3:%.*]] = trunc i32 [[T2]] to i16
-; CHECK-NEXT:    [[T4:%.*]] = add i16 [[Y]], -24
-; CHECK-NEXT:    [[T5:%.*]] = shl i16 [[T3]], [[T4]]
+; CHECK-NEXT:    [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
+; CHECK-NEXT:    [[T5:%.*]] = shl i16 [[X_TR]], 8
 ; CHECK-NEXT:    ret i16 [[T5]]
 ;
   %t0 = sub i16 32, %y
   %t1 = zext i16 %t0 to i32
   %t2 = shl i32 %x, %t1
   %t3 = trunc i32 %t2 to i16
   %t4 = add i16 %y, -24
   %t5 = shl i16 %t3, %t4
   ret i16 %t5
 }
 
 define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) {
 ; CHECK-LABEL: @t1_vec_splat(
-; CHECK-NEXT:    [[T0:%.*]] = sub <2 x i16> <i16 32, i16 32>, [[Y:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = zext <2 x i16> [[T0]] to <2 x i32>
-; CHECK-NEXT:    [[T2:%.*]] = shl <2 x i32> [[X:%.*]], [[T1]]
-; CHECK-NEXT:    [[T3:%.*]] = trunc <2 x i32> [[T2]] to <2 x i16>
-; CHECK-NEXT:    [[T4:%.*]] = add <2 x i16> [[Y]], <i16 -24, i16 -24>
-; CHECK-NEXT:    [[T5:%.*]] = shl <2 x i16> [[T3]], [[T4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 8, i32 8>
+; CHECK-NEXT:    [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
 ; CHECK-NEXT:    ret <2 x i16> [[T5]]
 ;
   %t0 = sub <2 x i16> <i16 32, i16 32>, %y
   %t1 = zext <2 x i16> %t0 to <2 x i32>
   %t2 = shl <2 x i32> %x, %t1
   %t3 = trunc <2 x i32> %t2 to <2 x i16>
   %t4 = add <2 x i16> %y, <i16 -24, i16 -24>
   %t5 = shl <2 x i16> %t3, %t4
   ret <2 x i16> %t5
 }
 
 define <2 x i16> @t2_vec_nonsplat(<2 x i32> %x, <2 x i16> %y) {
 ; CHECK-LABEL: @t2_vec_nonsplat(
-; CHECK-NEXT:    [[T0:%.*]] = sub <2 x i16> <i16 32, i16 30>, [[Y:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = zext <2 x i16> [[T0]] to <2 x i32>
-; CHECK-NEXT:    [[T2:%.*]] = shl <2 x i32> [[X:%.*]], [[T1]]
-; CHECK-NEXT:    [[T3:%.*]] = trunc <2 x i32> [[T2]] to <2 x i16>
-; CHECK-NEXT:    [[T4:%.*]] = add <2 x i16> [[Y]], <i16 -24, i16 0>
-; CHECK-NEXT:    [[T5:%.*]] = shl <2 x i16> [[T3]], [[T4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 8, i32 30>
+; CHECK-NEXT:    [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
 ; CHECK-NEXT:    ret <2 x i16> [[T5]]
 ;
   %t0 = sub <2 x i16> <i16 32, i16 30>, %y
   %t1 = zext <2 x i16> %t0 to <2 x i32>
   %t2 = shl <2 x i32> %x, %t1
   %t3 = trunc <2 x i32> %t2 to <2 x i16>
   %t4 = add <2 x i16> %y, <i16 -24, i16 0>
   %t5 = shl <2 x i16> %t3, %t4
   ret <2 x i16> %t5
 }
 
 ; Basic vector tests
 
 define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
 ; CHECK-LABEL: @t3_vec_nonsplat_undef0(
-; CHECK-NEXT:    [[T0:%.*]] = sub <3 x i16> <i16 32, i16 undef, i16 32>, [[Y:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = zext <3 x i16> [[T0]] to <3 x i32>
-; CHECK-NEXT:    [[T2:%.*]] = shl <3 x i32> [[X:%.*]], [[T1]]
-; CHECK-NEXT:    [[T3:%.*]] = trunc <3 x i32> [[T2]] to <3 x i16>
-; CHECK-NEXT:    [[T4:%.*]] = add <3 x i16> [[Y]], <i16 -24, i16 -24, i16 -24>
-; CHECK-NEXT:    [[T5:%.*]] = shl <3 x i16> [[T3]], [[T4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 8, i32 0, i32 8>
+; CHECK-NEXT:    [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
 ; CHECK-NEXT:    ret <3 x i16> [[T5]]
 ;
   %t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
   %t1 = zext <3 x i16> %t0 to <3 x i32>
   %t2 = shl <3 x i32> %x, %t1
   %t3 = trunc <3 x i32> %t2 to <3 x i16>
   %t4 = add <3 x i16> %y, <i16 -24, i16 -24, i16 -24>
   %t5 = shl <3 x i16> %t3, %t4
   ret <3 x i16> %t5
 }
 
 define <3 x i16> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
 ; CHECK-LABEL: @t4_vec_nonsplat_undef1(
-; CHECK-NEXT:    [[T0:%.*]] = sub <3 x i16> <i16 32, i16 32, i16 32>, [[Y:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = zext <3 x i16> [[T0]] to <3 x i32>
-; CHECK-NEXT:    [[T2:%.*]] = shl <3 x i32> [[X:%.*]], [[T1]]
-; CHECK-NEXT:    [[T3:%.*]] = trunc <3 x i32> [[T2]] to <3 x i16>
-; CHECK-NEXT:    [[T4:%.*]] = add <3 x i16> [[Y]], <i16 -24, i16 undef, i16 -24>
-; CHECK-NEXT:    [[T5:%.*]] = shl <3 x i16> [[T3]], [[T4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 8, i32 0, i32 8>
+; CHECK-NEXT:    [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
 ; CHECK-NEXT:    ret <3 x i16> [[T5]]
 ;
   %t0 = sub <3 x i16> <i16 32, i16 32, i16 32>, %y
   %t1 = zext <3 x i16> %t0 to <3 x i32>
   %t2 = shl <3 x i32> %x, %t1
   %t3 = trunc <3 x i32> %t2 to <3 x i16>
   %t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
   %t5 = shl <3 x i16> %t3, %t4
   ret <3 x i16> %t5
 }
 
 define <3 x i16> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
 ; CHECK-LABEL: @t5_vec_nonsplat_undef1(
-; CHECK-NEXT:    [[T0:%.*]] = sub <3 x i16> <i16 32, i16 undef, i16 32>, [[Y:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = zext <3 x i16> [[T0]] to <3 x i32>
-; CHECK-NEXT:    [[T2:%.*]] = shl <3 x i32> [[X:%.*]], [[T1]]
-; CHECK-NEXT:    [[T3:%.*]] = trunc <3 x i32> [[T2]] to <3 x i16>
-; CHECK-NEXT:    [[T4:%.*]] = add <3 x i16> [[Y]], <i16 -24, i16 undef, i16 -24>
-; CHECK-NEXT:    [[T5:%.*]] = shl <3 x i16> [[T3]], [[T4]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <3 x i32> [[X:%.*]], <i32 8, i32 0, i32 8>
+; CHECK-NEXT:    [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
 ; CHECK-NEXT:    ret <3 x i16> [[T5]]
 ;
   %t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
   %t1 = zext <3 x i16> %t0 to <3 x i32>
   %t2 = shl <3 x i32> %x, %t1
   %t3 = trunc <3 x i32> %t2 to <3 x i16>
   %t4 = add <3 x i16> %y, <i16 -24, i16 undef, i16 -24>
   %t5 = shl <3 x i16> %t3, %t4
   ret <3 x i16> %t5
 }
 
 ; One-use tests
 
 declare void @use16(i16)
 declare void @use32(i32)
 
 define i16 @t6_extrause0(i32 %x, i16 %y) {
 ; CHECK-LABEL: @t6_extrause0(
 ; CHECK-NEXT:    [[T0:%.*]] = sub i16 32, [[Y:%.*]]
 ; CHECK-NEXT:    [[T1:%.*]] = zext i16 [[T0]] to i32
 ; CHECK-NEXT:    [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
 ; CHECK-NEXT:    [[T3:%.*]] = trunc i32 [[T2]] to i16
-; CHECK-NEXT:    [[T4:%.*]] = add i16 [[Y]], -24
 ; CHECK-NEXT:    call void @use16(i16 [[T3]])
-; CHECK-NEXT:    [[T5:%.*]] = shl i16 [[T3]], [[T4]]
+; CHECK-NEXT:    [[X_TR:%.*]] = trunc i32 [[X]] to i16
+; CHECK-NEXT:    [[T5:%.*]] = shl i16 [[X_TR]], 8
 ; CHECK-NEXT:    ret i16 [[T5]]
 ;
   %t0 = sub i16 32, %y
   %t1 = zext i16 %t0 to i32
   %t2 = shl i32 %x, %t1
   %t3 = trunc i32 %t2 to i16
   %t4 = add i16 %y, -24
   call void @use16(i16 %t3)
   %t5 = shl i16 %t3, %t4
   ret i16 %t5
 }
 
 define i16 @t7_extrause1(i32 %x, i16 %y) {
 ; CHECK-LABEL: @t7_extrause1(
-; CHECK-NEXT:    [[T0:%.*]] = sub i16 32, [[Y:%.*]]
-; CHECK-NEXT:    [[T1:%.*]] = zext i16 [[T0]] to i32
-; CHECK-NEXT:    [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
-; CHECK-NEXT:    [[T3:%.*]] = trunc i32 [[T2]] to i16
-; CHECK-NEXT:    [[T4:%.*]] = add i16 [[Y]], -24
+; CHECK-NEXT:    [[T4:%.*]] = add i16 [[Y:%.*]], -24
 ; CHECK-NEXT:    call void @use16(i16 [[T4]])
-; CHECK-NEXT:    [[T5:%.*]] = shl i16 [[T3]], [[T4]]
+; CHECK-NEXT:    [[X_TR:%.*]] = trunc i32 [[X:%.*]] to i16
+; CHECK-NEXT:    [[T5:%.*]] = shl i16 [[X_TR]], 8
 ; CHECK-NEXT:    ret i16 [[T5]]
 ;
   %t0 = sub i16 32, %y
   %t1 = zext i16 %t0 to i32
   %t2 = shl i32 %x, %t1
   %t3 = trunc i32 %t2 to i16
   %t4 = add i16 %y, -24
   call void @use16(i16 %t4)