[AArch64][GlobalISel] Don't try to use GISel if subtarget doesn't have neon or fp.

[aemerson]

Summary

Throughout the legalizerinfo we currently make the assumption that the target has neon and FP target features available. Fixing it will require a refactor of the whole thing, so until then make sure we fall back.

Works around PR42734

[paquette]

LGTM

[jwf]

We're seeing a really odd regression with this diff. If you compile the following code with -target aarch64 -O0 -mgeneral-regs-only

#include <stdbool.h>
bool foo();
bool ice() {
  return foo();  // <- crashes the compiler during instruction selection
}

it crashes the compiler. If you instead make it

#include <stdbool.h>
bool foo();
bool ice() {
  bool b = foo();
  return b; 
}

then it is fine.

llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp

AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
   const LLT v8s16 = LLT::vector(8, 16);
   const LLT v4s16 = LLT::vector(4, 16);
   const LLT v2s16 = LLT::vector(2, 16);
   const LLT v2s32 = LLT::vector(2, 32);
   const LLT v4s32 = LLT::vector(4, 32);
   const LLT v2s64 = LLT::vector(2, 64);
   const LLT v2p0 = LLT::vector(2, p0);
 
+  // FIXME: support subtargets which have neon/fp-armv8 disabled.
+  if (!ST.hasNEON() || !ST.hasFPARMv8()) {
+    computeTables();
+    return;
+  }
+
   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
     .legalFor({p0, s1, s8, s16, s32, s64, v4s32, v2s64})
     .clampScalar(0, s1, s64)
     .widenScalarToNextPow2(0, 8)
     .fewerElementsIf(
       [=](const LegalityQuery &Query) {
         return Query.Types[0].isVector() &&
           (Query.Types[0].getElementType() != s64 ||

llvm/trunk/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll

+; RUN: not llc -o - -verify-machineinstrs -global-isel -global-isel-abort=1 -stop-after=legalizer %s 2>&1 | FileCheck %s
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-unknown"
+
+; CHECK: unable to legalize instruction: G_STORE %1:_(s128), %0:_(p0) :: (store 16 into %ir.ptr) (in function: foo)
+define void @foo(i128 *%ptr) #0 align 2 {
+entry:
+  store i128 0, i128* %ptr, align 16
+  ret void
+}
+
+attributes #0 = { "use-soft-float"="false" "target-features"="-fp-armv8,-neon" }
+