[AMDGPU] Increase kernel padding

[rampitec]

Summary

To support prefetch mode 3 we need to pad current
cacheline and fill 3 cachelines after. Current padding
is only sufficient for mode 2.

[rampitec]

Fixed count in test.

[kzhuravl]

LGTM

lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
   OS << StrOS.str() << '\n';
   OS << '\t' << V3::AssemblerDirectiveEnd << '\n';
   return true;
 }
 
 bool AMDGPUTargetAsmStreamer::EmitCodeEnd() {
   const uint32_t Encoded_s_code_end = 0xbf9f0000;
   OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n';
-  OS << "\t.fill 32, 4, " << Encoded_s_code_end << '\n';
+  OS << "\t.fill 48, 4, " << Encoded_s_code_end << '\n';
   return true;
 }
 
 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
     const MCSubtargetInfo &STI, StringRef KernelName,
     const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
     bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
   IsaVersion IVersion = getIsaVersion(STI.getCPU());

 }
 
 bool AMDGPUTargetELFStreamer::EmitCodeEnd() {
   const uint32_t Encoded_s_code_end = 0xbf9f0000;
 
   MCStreamer &OS = getStreamer();
   OS.PushSection();
   OS.EmitValueToAlignment(64, Encoded_s_code_end, 4);
-  for (unsigned I = 0; I < 32; ++I)
+  for (unsigned I = 0; I < 48; ++I)
     OS.EmitIntValue(Encoded_s_code_end, 4);
   OS.PopSection();
   return true;
 }
 
 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
     const MCSubtargetInfo &STI, StringRef KernelName,
     const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,

test/CodeGen/AMDGPU/s_code_end.ll

 ; GCN-ASM-NEXT:           .p2align        2
 ; GCN-ASM-NEXT:           .type   a_function,@function
 
 ; GCN-NEXT:       a_function:
 ; GCN:                    s_setpc_b64
 ; GCN-ASM-NEXT:   [[END_LABEL3:\.Lfunc_end.*]]:
 ; GCN-ASM-NEXT:           .size   a_function, [[END_LABEL3]]-a_function
 ; GFX10END-ASM:           .p2alignl 6, 3214868480
-; GFX10END-ASM-NEXT:      .fill 32, 4, 3214868480
+; GFX10END-ASM-NEXT:      .fill 48, 4, 3214868480
 ; GFX10NOEND-NOT:         .fill
 
 ; GFX10NOEND-OBJ-NOT:     s_code_end
 ; GFX10END-OBJ-NEXT:      s_code_end
 
 ; GFX10END-OBJ:           s_code_end // 000000000140:
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
-; GFX10END-OBJ-NEXT:      s_code_end
+; GFX10END-OBJ-NEXT-COUNT47: s_code_end
 
 define void @a_function() {
   ret void
 }