This is an archive of the discontinued LLVM Phabricator instance.

Differential D65158

[AMDGPU] Add all vgpr classes to asm parser
ClosedPublic

Authored by rampitec on Jul 23 2019, 11:08 AM.

Details

Reviewers
arsenm
tpr
dp
Commits
rG5cdacea29719: [AMDGPU] Add all vgpr classes to asm parser
rL366917: [AMDGPU] Add all vgpr classes to asm parser

Diff Detail

Event Timeline

rampitec created this revision.Jul 23 2019, 11:08 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptJul 23 2019, 11:08 AM
rampitec updated this revision to Diff 211349.Jul 23 2019, 12:28 PM
rampitec retitled this revision from [AMDGPU] Add all vgpr classes to AMDGPUOperand::isVReg() to [AMDGPU] Add all vgpr classes to asm parser.
rampitec edited the summary of this revision. (Show Details)
rampitec added a reviewer: tpr.

Found where it was a problem.

rampitec added a reviewer: dp.Jul 24 2019, 8:44 AM
dp accepted this revision.Jul 24 2019, 8:54 AM

LGTM

This revision is now accepted and ready to land.Jul 24 2019, 8:54 AM
Closed by commit rL366917: [AMDGPU] Add all vgpr classes to asm parser (authored by rampitec). · Explain WhyJul 24 2019, 9:21 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptJul 24 2019, 9:21 AM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
AsmParser/
4 lines

Diff 211337

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Show First 20 Lines • Show All 269 Lines • ▼ Show 20 Lines bool isRegOrImmWithFP64InputMods() const {
return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64); return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);
} }
bool isVReg() const { bool isVReg() const {
return isRegClass(AMDGPU::VGPR_32RegClassID) || return isRegClass(AMDGPU::VGPR_32RegClassID) ||
isRegClass(AMDGPU::VReg_64RegClassID) || isRegClass(AMDGPU::VReg_64RegClassID) ||
isRegClass(AMDGPU::VReg_96RegClassID) || isRegClass(AMDGPU::VReg_96RegClassID) ||
isRegClass(AMDGPU::VReg_128RegClassID) || isRegClass(AMDGPU::VReg_128RegClassID) ||
isRegClass(AMDGPU::VReg_160RegClassID) ||
isRegClass(AMDGPU::VReg_256RegClassID) || isRegClass(AMDGPU::VReg_256RegClassID) ||
isRegClass(AMDGPU::VReg_512RegClassID); isRegClass(AMDGPU::VReg_512RegClassID) ||
isRegClass(AMDGPU::VReg_1024RegClassID);
} }
bool isVReg32() const { bool isVReg32() const {
return isRegClass(AMDGPU::VGPR_32RegClassID); return isRegClass(AMDGPU::VGPR_32RegClassID);
} }
bool isVReg32OrOff() const { bool isVReg32OrOff() const {
return isOff() || isVReg32(); return isOff() || isVReg32();
▲ Show 20 Lines • Show All 6,616 Lines • Show Last 20 Lines