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[AArch64][SVE] Allow explicit size specifier for predicate operand
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Authored by chill on Jul 23 2019, 7:02 AM.

Details

Summary

... for the vector forms of {SQ,UQ,}{INC,DEC}P instructions. Also continue
supporting the existing behaviour of not requiring an explicit size
specifier. The preferred disassembly is *with* the specifier.

This is implemented by redefining instruction forms to require vector predicates
with explicit size and adding aliases, which allow a predicate with no size.

Diff Detail

Event Timeline

chill created this revision.Jul 23 2019, 7:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 23 2019, 7:02 AM
sdesmalen accepted this revision.Jul 25 2019, 3:43 AM

Thanks for this change @chill. LGTM.

llvm/lib/Target/AArch64/SVEInstrFormats.td
429

nit: for consistency with the rest of the file, can you group the InstAliases and move them below the definitions of the instructions?

This revision is now accepted and ready to land.Jul 25 2019, 3:43 AM
chill updated this revision to Diff 211735.Jul 25 2019, 6:21 AM
chill marked an inline comment as done.
This revision was automatically updated to reflect the committed changes.