This is an archive of the discontinued LLVM Phabricator instance.

Differential D65145

[AArch64][SVE] Allow explicit size specifier for predicate operand
ClosedPublic

Authored by chill on Jul 23 2019, 7:02 AM.

Details

Reviewers
sdesmalen
c-rhodes
t.p.northover
Commits
rGb77d4716f4b2: Merging r367019: --------------------------------------------------------------…
rL369086: Merging r367019:
rGa655f476b0eb: [AArch64][SVE] Allow explicit size specifier for predicate operand
rL367019: [AArch64][SVE] Allow explicit size specifier for predicate operand
Summary

... for the vector forms of {SQ,UQ,}{INC,DEC}P instructions. Also continue
supporting the existing behaviour of not requiring an explicit size
specifier. The preferred disassembly is *with* the specifier.

This is implemented by redefining instruction forms to require vector predicates
with explicit size and adding aliases, which allow a predicate with no size.

Diff Detail

Event Timeline

chill created this revision.Jul 23 2019, 7:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 23 2019, 7:02 AM
Herald added subscribers: llvm-commits, psnobl, rkruppe and 4 others. · View Herald Transcript
chill added reviewers: sdesmalen, c-rhodes, t.p.northover.Jul 23 2019, 7:04 AM
sdesmalen accepted this revision.Jul 25 2019, 3:43 AM

Thanks for this change @chill. LGTM.

llvm/lib/Target/AArch64/SVEInstrFormats.td
429

nit: for consistency with the rest of the file, can you group the InstAliases and move them below the definitions of the instructions?

This revision is now accepted and ready to land.Jul 25 2019, 3:43 AM
chill updated this revision to Diff 211735.Jul 25 2019, 6:21 AM
chill marked an inline comment as done.
Closed by commit rL367019: [AArch64][SVE] Allow explicit size specifier for predicate operand (authored by chill). · Explain WhyJul 25 2019, 6:55 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
24 lines
test/
MC/
AArch64/
SVE/
26 lines
28 lines
28 lines
28 lines
28 lines
28 lines

Diff 211291

llvm/lib/Target/AArch64/SVEInstrFormats.td

Show First 20 Lines • Show All 397 Lines • ▼ Show 20 Lines
multiclass sve_int_count_r_x64<bits<5> opc, string asm> { multiclass sve_int_count_r_x64<bits<5> opc, string asm> {
def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64z>; def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64z>;
def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>; def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>;
def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64z>; def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64z>;
def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64z>; def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64z>;
} }
class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm, class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
ZPRRegOp zprty> ZPRRegOp zprty, PPRRegOp pprty>
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, PPRAny:$Pg), : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, pprty:$Pm),
asm, "\t$Zdn, $Pg", asm, "\t$Zdn, $Pm",
"", "",
[]>, Sched<[]> { []>, Sched<[]> {
bits<4> Pg; bits<4> Pm;
bits<5> Zdn; bits<5> Zdn;
let Inst{31-24} = 0b00100101; let Inst{31-24} = 0b00100101;
let Inst{23-22} = sz8_64; let Inst{23-22} = sz8_64;
let Inst{21-19} = 0b101; let Inst{21-19} = 0b101;
let Inst{18-16} = opc{4-2}; let Inst{18-16} = opc{4-2};
let Inst{15-11} = 0b10000; let Inst{15-11} = 0b10000;
let Inst{10-9} = opc{1-0}; let Inst{10-9} = opc{1-0};
let Inst{8-5} = Pg; let Inst{8-5} = Pm;
let Inst{4-0} = Zdn; let Inst{4-0} = Zdn;
let Constraints = "$Zdn = $_Zdn"; let Constraints = "$Zdn = $_Zdn";
let DestructiveInstType = Destructive; let DestructiveInstType = Destructive;
let ElementSize = ElementSizeNone; let ElementSize = ElementSizeNone;
} }
multiclass sve_int_count_v<bits<5> opc, string asm> { multiclass sve_int_count_v<bits<5> opc, string asm> {
def _H : sve_int_count_v<0b01, opc, asm, ZPR16>; def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>;
def _S : sve_int_count_v<0b10, opc, asm, ZPR32>; def : InstAlias<asm # "\t$Zdn, $Pm",
sdesmalenUnsubmitted
Done
ReplyInline Actions

nit: for consistency with the rest of the file, can you group the InstAliases and move them below the definitions of the instructions?

sdesmalen: nit: for consistency with the rest of the file, can you group the InstAliases and move them…
def _D : sve_int_count_v<0b11, opc, asm, ZPR64>; (!cast<Instruction>(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>;
def _S : sve_int_count_v<0b10, opc, asm, ZPR32, PPR32>;
def : InstAlias<asm # "\t$Zdn, $Pm",
(!cast<Instruction>(NAME # "_S") ZPR32:$Zdn, PPRAny:$Pm), 0>;
def _D : sve_int_count_v<0b11, opc, asm, ZPR64, PPR64>;
def : InstAlias<asm # "\t$Zdn, $Pm",
(!cast<Instruction>(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>;
} }
class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm, class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm,
PPRRegOp pprty> PPRRegOp pprty>
: I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn), : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn),
asm, "\t$Rd, $Pg, $Pn", asm, "\t$Rd, $Pg, $Pn",
"", "",
[]>, Sched<[]> { []>, Sched<[]> {
▲ Show 20 Lines • Show All 5,278 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/SVE/decp.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
decp xzr, p15.d decp xzr, p15.d
// CHECK-INST: decp xzr, p15.d // CHECK-INST: decp xzr, p15.d
// CHECK-ENCODING: [0xff,0x89,0xed,0x25] // CHECK-ENCODING: [0xff,0x89,0xed,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 ed 25 <unknown> // CHECK-UNKNOWN: ff 89 ed 25 <unknown>
decp z31.h, p15 decp z31.h, p15
// CHECK-INST: decp z31.h, p15 // CHECK-INST: decp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6d 25 <unknown>
decp z31.h, p15.h
// CHECK-INST: decp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6d,0x25] // CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6d 25 <unknown> // CHECK-UNKNOWN: ff 81 6d 25 <unknown>
decp z31.s, p15 decp z31.s, p15
// CHECK-INST: decp z31.s, p15 // CHECK-INST: decp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xad,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ad 25 <unknown>
decp z31.s, p15.s
// CHECK-INST: decp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xad,0x25] // CHECK-ENCODING: [0xff,0x81,0xad,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ad 25 <unknown> // CHECK-UNKNOWN: ff 81 ad 25 <unknown>
decp z31.d, p15 decp z31.d, p15
// CHECK-INST: decp z31.d, p15 // CHECK-INST: decp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
decp z31.d, p15.d
// CHECK-INST: decp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xed,0x25] // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ed 25 <unknown> // CHECK-UNKNOWN: ff 81 ed 25 <unknown>
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction. // Test compatibility with MOVPRFX instruction.
movprfx z31, z6 movprfx z31, z6
// CHECK-INST: movprfx z31, z6 // CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown> // CHECK-UNKNOWN: df bc 20 04 <unknown>
decp z31.d, p15 decp z31.d, p15.d
// CHECK-INST: decp z31.d, p15 // CHECK-INST: decp z31.d, p15
// CHECK-ENCODING: [0xff,0x81,0xed,0x25] // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ed 25 <unknown> // CHECK-UNKNOWN: ff 81 ed 25 <unknown>

llvm/test/MC/AArch64/SVE/incp.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
incp xzr, p15.d incp xzr, p15.d
// CHECK-INST: incp xzr, p15.d // CHECK-INST: incp xzr, p15.d
// CHECK-ENCODING: [0xff,0x89,0xec,0x25] // CHECK-ENCODING: [0xff,0x89,0xec,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 ec 25 <unknown> // CHECK-UNKNOWN: ff 89 ec 25 <unknown>
incp z31.h, p15 incp z31.h, p15
// CHECK-INST: incp z31.h, p15 // CHECK-INST: incp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
incp z31.h, p15.h
// CHECK-INST: incp z31.h, p15.h
// CHECK-ENCODING: [0xff,0x81,0x6c,0x25] // CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 6c 25 <unknown> // CHECK-UNKNOWN: ff 81 6c 25 <unknown>
incp z31.s, p15 incp z31.s, p15
// CHECK-INST: incp z31.s, p15 // CHECK-INST: incp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xac,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
incp z31.s, p15.s
// CHECK-INST: incp z31.s, p15.s
// CHECK-ENCODING: [0xff,0x81,0xac,0x25] // CHECK-ENCODING: [0xff,0x81,0xac,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ac 25 <unknown> // CHECK-UNKNOWN: ff 81 ac 25 <unknown>
incp z31.d, p15 incp z31.d, p15
// CHECK-INST: incp z31.d, p15 // CHECK-INST: incp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
incp z31.d, p15.d
// CHECK-INST: incp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xec,0x25] // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown> // CHECK-UNKNOWN: ff 81 ec 25 <unknown>
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction. // Test compatibility with MOVPRFX instruction.
movprfx z31, z6 movprfx z31, z6
// CHECK-INST: movprfx z31, z6 // CHECK-INST: movprfx z31, z6
// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: df bc 20 04 <unknown> // CHECK-UNKNOWN: df bc 20 04 <unknown>
incp z31.d, p15 incp z31.d, p15.d
// CHECK-INST: incp z31.d, p15 // CHECK-INST: incp z31.d, p15.d
// CHECK-ENCODING: [0xff,0x81,0xec,0x25] // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 81 ec 25 <unknown> // CHECK-UNKNOWN: ff 81 ec 25 <unknown>

llvm/test/MC/AArch64/SVE/sqdecp.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
sqdecp xzr, p15.d, wzr sqdecp xzr, p15.d, wzr
// CHECK-INST: sqdecp xzr, p15.d, wzr // CHECK-INST: sqdecp xzr, p15.d, wzr
// CHECK-ENCODING: [0xff,0x89,0xea,0x25] // CHECK-ENCODING: [0xff,0x89,0xea,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 ea 25 <unknown> // CHECK-UNKNOWN: ff 89 ea 25 <unknown>
sqdecp z0.h, p0 sqdecp z0.h, p0
// CHECK-INST: sqdecp z0.h, p0 // CHECK-INST: sqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6a 25 <unknown>
sqdecp z0.h, p0.h
// CHECK-INST: sqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6a,0x25] // CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6a 25 <unknown> // CHECK-UNKNOWN: 00 80 6a 25 <unknown>
sqdecp z0.s, p0 sqdecp z0.s, p0
// CHECK-INST: sqdecp z0.s, p0 // CHECK-INST: sqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 aa 25 <unknown>
sqdecp z0.s, p0.s
// CHECK-INST: sqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xaa,0x25] // CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 aa 25 <unknown> // CHECK-UNKNOWN: 00 80 aa 25 <unknown>
sqdecp z0.d, p0 sqdecp z0.d, p0
// CHECK-INST: sqdecp z0.d, p0 // CHECK-INST: sqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
sqdecp z0.d, p0.d
// CHECK-INST: sqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xea,0x25] // CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown> // CHECK-UNKNOWN: 00 80 ea 25 <unknown>
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction. // Test compatibility with MOVPRFX instruction.
movprfx z0, z7 movprfx z0, z7
// CHECK-INST: movprfx z0, z7 // CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown> // CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqdecp z0.d, p0 sqdecp z0.d, p0.d
// CHECK-INST: sqdecp z0.d, p0 // CHECK-INST: sqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xea,0x25] // CHECK-ENCODING: [0x00,0x80,0xea,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ea 25 <unknown> // CHECK-UNKNOWN: 00 80 ea 25 <unknown>

llvm/test/MC/AArch64/SVE/sqincp.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
sqincp xzr, p15.d, wzr sqincp xzr, p15.d, wzr
// CHECK-INST: sqincp xzr, p15.d, wzr // CHECK-INST: sqincp xzr, p15.d, wzr
// CHECK-ENCODING: [0xff,0x89,0xe8,0x25] // CHECK-ENCODING: [0xff,0x89,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 e8 25 <unknown> // CHECK-UNKNOWN: ff 89 e8 25 <unknown>
sqincp z0.h, p0 sqincp z0.h, p0
// CHECK-INST: sqincp z0.h, p0 // CHECK-INST: sqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x68,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 68 25 <unknown>
sqincp z0.h, p0.h
// CHECK-INST: sqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x68,0x25] // CHECK-ENCODING: [0x00,0x80,0x68,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 68 25 <unknown> // CHECK-UNKNOWN: 00 80 68 25 <unknown>
sqincp z0.s, p0 sqincp z0.s, p0
// CHECK-INST: sqincp z0.s, p0 // CHECK-INST: sqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
sqincp z0.s, p0.s
// CHECK-INST: sqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa8,0x25] // CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a8 25 <unknown> // CHECK-UNKNOWN: 00 80 a8 25 <unknown>
sqincp z0.d, p0 sqincp z0.d, p0
// CHECK-INST: sqincp z0.d, p0 // CHECK-INST: sqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
sqincp z0.d, p0.d
// CHECK-INST: sqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25] // CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown> // CHECK-UNKNOWN: 00 80 e8 25 <unknown>
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction. // Test compatibility with MOVPRFX instruction.
movprfx z0, z7 movprfx z0, z7
// CHECK-INST: movprfx z0, z7 // CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown> // CHECK-UNKNOWN: e0 bc 20 04 <unknown>
sqincp z0.d, p0 sqincp z0.d, p0.d
// CHECK-INST: sqincp z0.d, p0 // CHECK-INST: sqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe8,0x25] // CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e8 25 <unknown> // CHECK-UNKNOWN: 00 80 e8 25 <unknown>

llvm/test/MC/AArch64/SVE/uqdecp.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
uqdecp wzr, p15.d uqdecp wzr, p15.d
// CHECK-INST: uqdecp wzr, p15.d // CHECK-INST: uqdecp wzr, p15.d
// CHECK-ENCODING: [0xff,0x89,0xeb,0x25] // CHECK-ENCODING: [0xff,0x89,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 eb 25 <unknown> // CHECK-UNKNOWN: ff 89 eb 25 <unknown>
uqdecp z0.h, p0 uqdecp z0.h, p0
// CHECK-INST: uqdecp z0.h, p0 // CHECK-INST: uqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6b 25 <unknown>
uqdecp z0.h, p0.h
// CHECK-INST: uqdecp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x6b,0x25] // CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 6b 25 <unknown> // CHECK-UNKNOWN: 00 80 6b 25 <unknown>
uqdecp z0.s, p0 uqdecp z0.s, p0
// CHECK-INST: uqdecp z0.s, p0 // CHECK-INST: uqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xab,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ab 25 <unknown>
uqdecp z0.s, p0.s
// CHECK-INST: uqdecp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xab,0x25] // CHECK-ENCODING: [0x00,0x80,0xab,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 ab 25 <unknown> // CHECK-UNKNOWN: 00 80 ab 25 <unknown>
uqdecp z0.d, p0 uqdecp z0.d, p0
// CHECK-INST: uqdecp z0.d, p0 // CHECK-INST: uqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
uqdecp z0.d, p0.d
// CHECK-INST: uqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25] // CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown> // CHECK-UNKNOWN: 00 80 eb 25 <unknown>
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction. // Test compatibility with MOVPRFX instruction.
movprfx z0, z7 movprfx z0, z7
// CHECK-INST: movprfx z0, z7 // CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown> // CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqdecp z0.d, p0 uqdecp z0.d, p0.d
// CHECK-INST: uqdecp z0.d, p0 // CHECK-INST: uqdecp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xeb,0x25] // CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 eb 25 <unknown> // CHECK-UNKNOWN: 00 80 eb 25 <unknown>

llvm/test/MC/AArch64/SVE/uqincp.s

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
uqincp wzr, p15.d uqincp wzr, p15.d
// CHECK-INST: uqincp wzr, p15.d // CHECK-INST: uqincp wzr, p15.d
// CHECK-ENCODING: [0xff,0x89,0xe9,0x25] // CHECK-ENCODING: [0xff,0x89,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 89 e9 25 <unknown> // CHECK-UNKNOWN: ff 89 e9 25 <unknown>
uqincp z0.h, p0 uqincp z0.h, p0
// CHECK-INST: uqincp z0.h, p0 // CHECK-INST: uqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x69,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 69 25 <unknown>
uqincp z0.h, p0.h
// CHECK-INST: uqincp z0.h, p0.h
// CHECK-ENCODING: [0x00,0x80,0x69,0x25] // CHECK-ENCODING: [0x00,0x80,0x69,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 69 25 <unknown> // CHECK-UNKNOWN: 00 80 69 25 <unknown>
uqincp z0.s, p0 uqincp z0.s, p0
// CHECK-INST: uqincp z0.s, p0 // CHECK-INST: uqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a9 25 <unknown>
uqincp z0.s, p0.s
// CHECK-INST: uqincp z0.s, p0.s
// CHECK-ENCODING: [0x00,0x80,0xa9,0x25] // CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 a9 25 <unknown> // CHECK-UNKNOWN: 00 80 a9 25 <unknown>
uqincp z0.d, p0 uqincp z0.d, p0
// CHECK-INST: uqincp z0.d, p0 // CHECK-INST: uqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
uqincp z0.d, p0.d
// CHECK-INST: uqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25] // CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown> // CHECK-UNKNOWN: 00 80 e9 25 <unknown>
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction. // Test compatibility with MOVPRFX instruction.
movprfx z0, z7 movprfx z0, z7
// CHECK-INST: movprfx z0, z7 // CHECK-INST: movprfx z0, z7
// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 bc 20 04 <unknown> // CHECK-UNKNOWN: e0 bc 20 04 <unknown>
uqincp z0.d, p0 uqincp z0.d, p0.d
// CHECK-INST: uqincp z0.d, p0 // CHECK-INST: uqincp z0.d, p0.d
// CHECK-ENCODING: [0x00,0x80,0xe9,0x25] // CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
// CHECK-ERROR: instruction requires: sve // CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 80 e9 25 <unknown> // CHECK-UNKNOWN: 00 80 e9 25 <unknown>