[libunwind][ARM] Fix loading FP registers on big-endian targets

[miyuki]

Summary

The function Unwind-EHABI.cpp:_Unwind_VRS_Pop loads the saved values of
64-bit FP registers as two 32-bit words because they might not be
8-byte aligned. Combining these words into a 64-bit value has to be
done differently on big-endian platforms.

[ostannard]

LGTM

libunwind/src/Unwind-EHABI.cpp

case _UVRSC_VFP: {
       if (_Unwind_VRS_Get(context, _UVRSC_CORE, UNW_ARM_SP,
                           _UVRSD_UINT32, &sp) != _UVRSR_OK) {
         return _UVRSR_FAILED;
       }
       // For _UVRSD_VFPX, we're assuming the data is stored in FSTMX "standard
       // format 1", which is equivalent to FSTMD + a padding word.
       for (uint32_t i = first; i < end; ++i) {
         // SP is only 32-bit aligned so don't copy 64-bit at a time.
-        uint64_t value = *sp++;
-        value |= ((uint64_t)(*sp++)) << 32;
+        uint32_t w0 = *sp++;
+        uint32_t w1 = *sp++;
+#ifdef __LITTLE_ENDIAN__
+        uint64_t value = (w1 << 32) | w0;
+#else
+        uint64_t value = (w0 << 32) | w1;
+#endif
         if (_Unwind_VRS_Set(context, regclass, i, representation, &value) !=
             _UVRSR_OK)
           return _UVRSR_FAILED;
       }
       if (representation == _UVRSD_VFPX)
         ++sp;
       return _Unwind_VRS_Set(context, _UVRSC_CORE, UNW_ARM_SP, _UVRSD_UINT32,
                              &sp);