AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR

[tstellar]

LGTM.

[tstellar]

lib/Target/AMDGPU/AMDGPUInstructionSelector.h

75

Would we be able to do this in TableGen if we didn't have to special case the boolean values?

[arsenm]

lib/Target/AMDGPU/AMDGPUInstructionSelector.h

75

I think so

[arsenm]

r366121

lib/Target/AMDGPU/AMDGPUInstructionSelector.h

private:
 
   MachineOperand getSubOperand64(MachineOperand &MO,
                                  const TargetRegisterClass &SubRC,
                                  unsigned SubIdx) const;
   bool selectCOPY(MachineInstr &I) const;
   bool selectPHI(MachineInstr &I) const;
   bool selectG_TRUNC(MachineInstr &I) const;
   bool selectG_SZA_EXT(MachineInstr &I) const;
   bool selectG_CONSTANT(MachineInstr &I) const;
+  bool selectG_AND_OR_XOR(MachineInstr &I) const;
   bool selectG_ADD_SUB(MachineInstr &I) const;
   bool selectG_EXTRACT(MachineInstr &I) const;
   bool selectG_MERGE_VALUES(MachineInstr &I) const;
   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
   bool selectG_GEP(MachineInstr &I) const;
   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
   bool selectG_INSERT(MachineInstr &I) const;
   bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 static bool isSCC(Register Reg, const MachineRegisterInfo &MRI) {
   if (TargetRegisterInfo::isPhysicalRegister(Reg))
     return Reg == AMDGPU::SCC;
 
   auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
   const TargetRegisterClass *RC =
       RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
   if (RC) {
+    // FIXME: This is ambiguous for wave32. This could be SCC or VCC, but the
+    // context of the register bank has been lost.
     if (RC->getID() != AMDGPU::SReg_32_XM0RegClassID)
       return false;
     const LLT Ty = MRI.getType(Reg);
     return Ty.isValid() && Ty.getSizeInBits() == 1;
   }
 
   const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
   return RB->getID() == AMDGPU::SCCRegBankID;
case AMDGPU::sub1:
     return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
   }
 }
 
 static int64_t getConstant(const MachineInstr *MI) {
   return MI->getOperand(1).getCImm()->getSExtValue();
 }
 
+static unsigned getLogicalBitOpcode(unsigned Opc, bool Is64) {
+  switch (Opc) {
+  case AMDGPU::G_AND:
+    return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32;
+  case AMDGPU::G_OR:
+    return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32;
+  case AMDGPU::G_XOR:
+    return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32;
+  default:
+    llvm_unreachable("not a bit op");
+  }
+}
+
+bool AMDGPUInstructionSelector::selectG_AND_OR_XOR(MachineInstr &I) const {
+  MachineBasicBlock *BB = I.getParent();
+  MachineFunction *MF = BB->getParent();
+  MachineRegisterInfo &MRI = MF->getRegInfo();
+  MachineOperand &Dst = I.getOperand(0);
+  MachineOperand &Src0 = I.getOperand(1);
+  MachineOperand &Src1 = I.getOperand(2);
+  Register DstReg = Dst.getReg();
+  unsigned Size = RBI.getSizeInBits(DstReg, MRI, TRI);
+
+  const RegisterBank *DstRB = RBI.getRegBank(DstReg, MRI, TRI);
+  if (DstRB->getID() == AMDGPU::VCCRegBankID) {
+    const TargetRegisterClass *RC = TRI.getBoolRC();
+    unsigned InstOpc = getLogicalBitOpcode(I.getOpcode(),
+                                           RC == &AMDGPU::SReg_64RegClass);
+    I.setDesc(TII.get(InstOpc));
+
+    // FIXME: Hack to avoid turning the register bank into a register class.
+    // The selector for G_ICMP relies on seeing the register bank for the result
+    // is VCC. In wave32 if we constrain the registers to SReg_32 here, it will
+    // be ambiguous whether it's a scalar or vector bool.
+    if (Src0.isUndef() && !MRI.getRegClassOrNull(Src0.getReg()))
+      MRI.setRegClass(Src0.getReg(), RC);
+    if (Src1.isUndef() && !MRI.getRegClassOrNull(Src1.getReg()))
+      MRI.setRegClass(Src1.getReg(), RC);
+
+    return RBI.constrainGenericRegister(DstReg, *RC, MRI);
+  }
+
+  // TODO: Should this allow an SCC bank result, and produce a copy from SCC for
+  // the result?
+  if (DstRB->getID() == AMDGPU::SGPRRegBankID) {
+    const TargetRegisterClass *RC
+      = TRI.getConstrainedRegClassForOperand(Dst, MRI);
+    unsigned InstOpc = getLogicalBitOpcode(I.getOpcode(), Size > 32);
+    I.setDesc(TII.get(InstOpc));
+    return RBI.constrainGenericRegister(DstReg, *RC, MRI) &&
+           RBI.constrainGenericRegister(Src0.getReg(), *RC, MRI) &&
+           RBI.constrainGenericRegister(Src1.getReg(), *RC, MRI);
+  }
+
+  return false;
+}
+
 bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
   MachineBasicBlock *BB = I.getParent();
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
   Register DstReg = I.getOperand(0).getReg();
   const DebugLoc &DL = I.getDebugLoc();
   unsigned Size = RBI.getSizeInBits(DstReg, MRI, TRI);
   const RegisterBank *DstRB = RBI.getRegBank(DstReg, MRI, TRI);
bool AMDGPUInstructionSelector::select(MachineInstr &I,
 
   if (!isPreISelGenericOpcode(I.getOpcode())) {
     if (I.isCopy())
       return selectCOPY(I);
     return true;
   }
 
   switch (I.getOpcode()) {
+  case TargetOpcode::G_AND:
+  case TargetOpcode::G_OR:
+  case TargetOpcode::G_XOR:
+    if (selectG_AND_OR_XOR(I))
+      return true;
+    return selectImpl(I, CoverageInfo);
   case TargetOpcode::G_ADD:
   case TargetOpcode::G_SUB:
     if (selectG_ADD_SUB(I))
       return true;
     LLVM_FALLTHROUGH;
   default:
     return selectImpl(I, CoverageInfo);
   case TargetOpcode::G_INTTOPTR:

test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s
+
+---
+
+name:            and_s1_vcc_vcc_vcc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: and_s1_vcc_vcc_vcc
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
+    ; WAVE32-LABEL: name: and_s1_vcc_vcc_vcc
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = G_CONSTANT i32 0
+    %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
+    %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
+    %5:vcc(s1) = G_AND %3, %4
+    S_ENDPGM 0, implicit %5
+...
+
+---
+
+name:            and_s1_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: and_s1_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    ; WAVE32-LABEL: name: and_s1_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s1) = G_TRUNC %0
+    %3:sgpr(s1) = G_TRUNC %1
+    %4:sgpr(s1) = G_AND %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            and_s1_scc_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: and_s1_scc_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+    ; WAVE64: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[AND]](s1)
+    ; WAVE32-LABEL: name: and_s1_scc_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+    ; WAVE32: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[AND]](s1)
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s1) = G_TRUNC %0
+    %3:sgpr(s1) = G_TRUNC %1
+    %4:scc(s1) = G_AND %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            and_s16_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: and_s16_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE64: [[AND:%[0-9]+]]:sgpr(s16) = G_AND [[TRUNC]], [[TRUNC1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[AND]](s16)
+    ; WAVE32-LABEL: name: and_s16_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE32: [[AND:%[0-9]+]]:sgpr(s16) = G_AND [[TRUNC]], [[TRUNC1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[AND]](s16)
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s16) = G_TRUNC %0
+    %3:sgpr(s16) = G_TRUNC %1
+    %4:sgpr(s16) = G_AND %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            and_s16_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: and_s16_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE64: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[TRUNC]], [[TRUNC1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[AND]](s16)
+    ; WAVE32-LABEL: name: and_s16_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE32: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[TRUNC]], [[TRUNC1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[AND]](s16)
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s16) = G_TRUNC %0
+    %3:vgpr(s16) = G_TRUNC %1
+    %4:vgpr(s16) = G_AND %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            and_s32_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: and_s32_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    ; WAVE32-LABEL: name: and_s32_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s32) = G_AND %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_s64_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64-LABEL: name: and_s64_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
+    ; WAVE32-LABEL: name: and_s64_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE32: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B64_]]
+    %0:sgpr(s64) = COPY $sgpr0_sgpr1
+    %1:sgpr(s64) = COPY $sgpr2_sgpr3
+    %2:sgpr(s64) = G_AND %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_v2s16_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: and_v2s16_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    ; WAVE32-LABEL: name: and_v2s16_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    %0:sgpr(<2 x s16>) = COPY $sgpr0
+    %1:sgpr(<2 x s16>) = COPY $sgpr1
+    %2:sgpr(<2 x s16>) = G_AND %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_v2s32_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64-LABEL: name: and_v2s32_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
+    ; WAVE32-LABEL: name: and_v2s32_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE32: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B64_]]
+    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
+    %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
+    %2:sgpr(<2 x s32>) = G_AND %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_v4s16_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64-LABEL: name: and_v4s16_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
+    ; WAVE32-LABEL: name: and_v4s16_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE32: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B64_]]
+    %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+    %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
+    %2:sgpr(<4 x s16>) = G_AND %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_s32_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: and_s32_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE64: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE64: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
+    ; WAVE32-LABEL: name: and_s32_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = G_AND %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_v2s16_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: and_v2s16_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+    ; WAVE64: [[AND:%[0-9]+]]:vgpr(<2 x s16>) = G_AND [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[AND]](<2 x s16>)
+    ; WAVE32-LABEL: name: and_v2s16_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+    ; WAVE32: [[AND:%[0-9]+]]:vgpr(<2 x s16>) = G_AND [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[AND]](<2 x s16>)
+    %0:vgpr(<2 x s16>) = COPY $vgpr0
+    %1:vgpr(<2 x s16>) = COPY $vgpr1
+    %2:vgpr(<2 x s16>) = G_AND %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+
+# This should fail to select
+---
+
+name:            and_s64_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; WAVE64-LABEL: name: and_s64_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+    ; WAVE64: [[AND:%[0-9]+]]:vgpr(s64) = G_AND [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[AND]](s64)
+    ; WAVE32-LABEL: name: and_s64_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+    ; WAVE32: [[AND:%[0-9]+]]:vgpr(s64) = G_AND [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[AND]](s64)
+    %0:vgpr(s64) = COPY $vgpr0_vgpr1
+    %1:vgpr(s64) = COPY $vgpr2_vgpr3
+    %2:vgpr(s64) = G_AND %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_s1_vcc_undef_vcc_undef_vcc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    ; WAVE64-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc
+    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 undef %1:sreg_64, undef %2:sreg_64
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
+    ; WAVE32-LABEL: name: and_s1_vcc_undef_vcc_undef_vcc
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    %2:vcc(s1) = G_AND undef %0:vcc(s1), undef %1:vcc(s1)
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_s1_sgpr_undef_sgpr_undef_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    ; WAVE64-LABEL: name: and_s1_sgpr_undef_sgpr_undef_sgpr
+    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    ; WAVE32-LABEL: name: and_s1_sgpr_undef_sgpr_undef_sgpr
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    %2:sgpr(s1) = G_AND undef %0:sgpr(s1), undef %1:sgpr(s1)
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_s1_vgpr_undef_vgpr_undef_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    ; WAVE64-LABEL: name: and_s1_vgpr_undef_vgpr_undef_vgpr
+    ; WAVE64: [[AND:%[0-9]+]]:vgpr(s1) = G_AND undef %1:vgpr, undef %2:vgpr
+    ; WAVE64: S_ENDPGM 0, implicit [[AND]](s1)
+    ; WAVE32-LABEL: name: and_s1_vgpr_undef_vgpr_undef_vgpr
+    ; WAVE32: [[AND:%[0-9]+]]:vgpr(s1) = G_AND undef %1:vgpr, undef %2:vgpr
+    ; WAVE32: S_ENDPGM 0, implicit [[AND]](s1)
+    %2:vgpr(s1) = G_AND undef %0:vgpr(s1), undef %1:vgpr(s1)
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            and_s1_vcc_copy_to_vcc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: and_s1_vcc_copy_to_vcc
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
+    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
+    ; WAVE32-LABEL: name: and_s1_vcc_copy_to_vcc
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
+    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s1) = G_TRUNC %0
+    %3:vgpr(s1) = G_TRUNC %1
+    %4:vcc(s1) = COPY %2
+    %5:vcc(s1) = COPY %3
+    %6:vcc(s1) = G_AND %4, %5
+    S_ENDPGM 0, implicit %6
+...
+
+# The selector for the copy of the and result may constrain the result
+# register of the and, losing that it is a VCCRegBank context.
+
+# Works for wave32, should fail for wave64
+---
+name:            copy_select_constrain_vcc_result_reg_wave32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
+    ; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; WAVE64: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
+    ; WAVE64: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; WAVE64: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
+    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_64_xexec(s1) = S_AND_B32 [[COPY1]](s1), [[COPY2]](s1)
+    ; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0(s1) = COPY [[S_AND_B32_]](s1)
+    ; WAVE64: S_ENDPGM 0, implicit [[COPY3]](s1)
+    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
+    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
+    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
+    %1:vgpr(s32) = COPY $vgpr0
+    %0:vgpr(s1) = G_TRUNC %1(s32)
+    %2:sgpr(s1) = G_CONSTANT i1 true
+    %6:sgpr(s32) = G_CONSTANT i32 0
+    %7:sgpr(p1) = G_IMPLICIT_DEF
+    %9:vcc(s1) = COPY %0(s1)
+    %10:vcc(s1) = COPY %2(s1)
+    %8:vcc(s1) = G_AND %9, %10
+    %3:sreg_32_xm0(s1) = COPY %8(s1)
+    S_ENDPGM 0, implicit %3
+
+...
+
+# Works for wave64, should fail for wave32
+---
+name:            copy_select_constrain_vcc_result_reg_wave64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
+    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
+    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B64_]]
+    ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
+    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
+    ; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; WAVE32: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
+    ; WAVE32: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; WAVE32: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
+    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 [[COPY1]](s1), [[COPY2]](s1)
+    ; WAVE32: [[COPY3:%[0-9]+]]:sreg_64_xexec(s1) = COPY [[S_AND_B32_]](s1)
+    ; WAVE32: S_ENDPGM 0, implicit [[COPY3]](s1)
+    %1:vgpr(s32) = COPY $vgpr0
+    %0:vgpr(s1) = G_TRUNC %1(s32)
+    %2:sgpr(s1) = G_CONSTANT i1 true
+    %6:sgpr(s32) = G_CONSTANT i32 0
+    %7:sgpr(p1) = G_IMPLICIT_DEF
+    %9:vcc(s1) = COPY %0(s1)
+    %10:vcc(s1) = COPY %2(s1)
+    %8:vcc(s1) = G_AND %9, %10
+    %3:sreg_64_xexec(s1) = COPY %8(s1)
+    S_ENDPGM 0, implicit %3
+
+...

test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s -check-prefixes=GCN
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s
 
 ---
 
-name:            or
+name:            or_s1_vcc_vcc_vcc
 legalized:       true
 regBankSelected: true
+tracksRegLiveness: true
 
-# GCN-LABEL: name: or
 body: |
   bb.0:
-    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
-    ; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
-    ; GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
-    ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: or_s1_vcc_vcc_vcc
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
+    ; WAVE32-LABEL: name: or_s1_vcc_vcc_vcc
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = G_CONSTANT i32 0
+    %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
+    %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
+    %5:vcc(s1) = G_OR %3, %4
+    S_ENDPGM 0, implicit %5
+...
+
+---
+
+name:            or_s1_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: or_s1_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    ; WAVE32-LABEL: name: or_s1_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s1) = G_TRUNC %0
+    %3:sgpr(s1) = G_TRUNC %1
+    %4:sgpr(s1) = G_OR %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            or_s1_scc_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: or_s1_scc_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+    ; WAVE64: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[OR]](s1)
+    ; WAVE32-LABEL: name: or_s1_scc_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+    ; WAVE32: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[OR]](s1)
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s1) = G_TRUNC %0
+    %3:sgpr(s1) = G_TRUNC %1
+    %4:scc(s1) = G_OR %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            or_s16_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: or_s16_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE64: [[OR:%[0-9]+]]:sgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[OR]](s16)
+    ; WAVE32-LABEL: name: or_s16_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE32: [[OR:%[0-9]+]]:sgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[OR]](s16)
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s16) = G_TRUNC %0
+    %3:sgpr(s16) = G_TRUNC %1
+    %4:sgpr(s16) = G_OR %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            or_s16_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: or_s16_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE64: [[OR:%[0-9]+]]:vgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[OR]](s16)
+    ; WAVE32-LABEL: name: or_s16_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE32: [[OR:%[0-9]+]]:vgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[OR]](s16)
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s16) = G_TRUNC %0
+    %3:vgpr(s16) = G_TRUNC %1
+    %4:vgpr(s16) = G_OR %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            or_s32_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: or_s32_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    ; WAVE32-LABEL: name: or_s32_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1
-    %2:vgpr(s32) = COPY $vgpr0
-    %3:vgpr(p1) = COPY $vgpr3_vgpr4
-    %4:sgpr(s32) = G_CONSTANT i32 1
-    %5:sgpr(s32) = G_CONSTANT i32 4096
-
-    ; or ss
-    ; GCN: [[SS:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[SGPR0]], [[SGPR1]]
-    %6:sgpr(s32) = G_OR %0, %1
-
-    ; or vs
-    ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VGPR0]]
-    %7:vgpr(s32) = G_OR %2, %6
-
-    ; or sv
-    ; GCN: [[SV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VS]]
-    %8:vgpr(s32) = G_OR %6, %7
-
-    ; or vv
-    ; GCN: [[VV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SV]], [[VGPR0]]
-    %9:vgpr(s32) = G_OR %8, %2
+    %2:sgpr(s32) = G_OR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_s64_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64-LABEL: name: or_s64_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
+    ; WAVE32-LABEL: name: or_s64_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
+    %0:sgpr(s64) = COPY $sgpr0_sgpr1
+    %1:sgpr(s64) = COPY $sgpr2_sgpr3
+    %2:sgpr(s64) = G_OR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_v2s16_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    ; WAVE32-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    %0:sgpr(<2 x s16>) = COPY $sgpr0
+    %1:sgpr(<2 x s16>) = COPY $sgpr1
+    %2:sgpr(<2 x s16>) = G_OR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_v2s32_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
+    ; WAVE32-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
+    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
+    %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
+    %2:sgpr(<2 x s32>) = G_OR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_v4s16_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
+    ; WAVE32-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE32: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B64_]]
+    %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+    %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
+    %2:sgpr(<4 x s16>) = G_OR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_s32_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: or_s32_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE64: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE64: S_ENDPGM 0, implicit [[V_OR_B32_e32_]]
+    ; WAVE32-LABEL: name: or_s32_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE32: S_ENDPGM 0, implicit [[V_OR_B32_e32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = G_OR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_v2s16_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+    ; WAVE64: [[OR:%[0-9]+]]:vgpr(<2 x s16>) = G_OR [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[OR]](<2 x s16>)
+    ; WAVE32-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+    ; WAVE32: [[OR:%[0-9]+]]:vgpr(<2 x s16>) = G_OR [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[OR]](<2 x s16>)
+    %0:vgpr(<2 x s16>) = COPY $vgpr0
+    %1:vgpr(<2 x s16>) = COPY $vgpr1
+    %2:vgpr(<2 x s16>) = G_OR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+
+# This should fail to select
+---
+
+name:            or_s64_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; WAVE64-LABEL: name: or_s64_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+    ; WAVE64: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[OR]](s64)
+    ; WAVE32-LABEL: name: or_s64_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+    ; WAVE32: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[OR]](s64)
+    %0:vgpr(s64) = COPY $vgpr0_vgpr1
+    %1:vgpr(s64) = COPY $vgpr2_vgpr3
+    %2:vgpr(s64) = G_OR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_s1_vcc_undef_vcc_undef_vcc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    ; WAVE64-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
+    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 undef %1:sreg_64, undef %2:sreg_64
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
+    ; WAVE32-LABEL: name: or_s1_vcc_undef_vcc_undef_vcc
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    %2:vcc(s1) = G_OR undef %0:vcc(s1), undef %1:vcc(s1)
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_s1_sgpr_undef_sgpr_undef_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    ; WAVE64-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
+    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    ; WAVE32-LABEL: name: or_s1_sgpr_undef_sgpr_undef_sgpr
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    %2:sgpr(s1) = G_OR undef %0:sgpr(s1), undef %1:sgpr(s1)
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_s1_vgpr_undef_vgpr_undef_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    ; WAVE64-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
+    ; WAVE64: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
+    ; WAVE64: S_ENDPGM 0, implicit [[OR]](s1)
+    ; WAVE32-LABEL: name: or_s1_vgpr_undef_vgpr_undef_vgpr
+    ; WAVE32: [[OR:%[0-9]+]]:vgpr(s1) = G_OR undef %1:vgpr, undef %2:vgpr
+    ; WAVE32: S_ENDPGM 0, implicit [[OR]](s1)
+    %2:vgpr(s1) = G_OR undef %0:vgpr(s1), undef %1:vgpr(s1)
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            or_s1_vcc_copy_to_vcc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: or_s1_vcc_copy_to_vcc
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
+    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B64_]]
+    ; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
+    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s1) = G_TRUNC %0
+    %3:vgpr(s1) = G_TRUNC %1
+    %4:vcc(s1) = COPY %2
+    %5:vcc(s1) = COPY %3
+    %6:vcc(s1) = G_OR %4, %5
+    S_ENDPGM 0, implicit %6
+...
+
+# The selector for the copy of the or result may constrain the result
+# register of the or, losing that it is a VCCRegBank context.
+
+# Works for wave32, should fail for wave64
+---
+name:            copy_select_constrain_vcc_result_reg_wave32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
+    ; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; WAVE64: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
+    ; WAVE64: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; WAVE64: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
+    ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_64_xexec(s1) = S_OR_B32 [[COPY1]](s1), [[COPY2]](s1)
+    ; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0(s1) = COPY [[S_OR_B32_]](s1)
+    ; WAVE64: S_ENDPGM 0, implicit [[COPY3]](s1)
+    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
+    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
+    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
+    %1:vgpr(s32) = COPY $vgpr0
+    %0:vgpr(s1) = G_TRUNC %1(s32)
+    %2:sgpr(s1) = G_CONSTANT i1 true
+    %6:sgpr(s32) = G_CONSTANT i32 0
+    %7:sgpr(p1) = G_IMPLICIT_DEF
+    %9:vcc(s1) = COPY %0(s1)
+    %10:vcc(s1) = COPY %2(s1)
+    %8:vcc(s1) = G_OR %9, %10
+    %3:sreg_32_xm0(s1) = COPY %8(s1)
+    S_ENDPGM 0, implicit %3
+
+...
+
+# Works for wave64, should fail for wave32
+---
+name:            copy_select_constrain_vcc_result_reg_wave64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
 
-    G_STORE %9, %3 :: (store 4, addrspace 1)
+    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
+    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
+    ; WAVE64: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B64_]]
+    ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
+    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
+    ; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; WAVE32: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
+    ; WAVE32: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; WAVE32: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
+    ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[COPY1]](s1), [[COPY2]](s1)
+    ; WAVE32: [[COPY3:%[0-9]+]]:sreg_64_xexec(s1) = COPY [[S_OR_B32_]](s1)
+    ; WAVE32: S_ENDPGM 0, implicit [[COPY3]](s1)
+    %1:vgpr(s32) = COPY $vgpr0
+    %0:vgpr(s1) = G_TRUNC %1(s32)
+    %2:sgpr(s1) = G_CONSTANT i1 true
+    %6:sgpr(s32) = G_CONSTANT i32 0
+    %7:sgpr(p1) = G_IMPLICIT_DEF
+    %9:vcc(s1) = COPY %0(s1)
+    %10:vcc(s1) = COPY %2(s1)
+    %8:vcc(s1) = G_OR %9, %10
+    %3:sreg_64_xexec(s1) = COPY %8(s1)
+    S_ENDPGM 0, implicit %3
 
 ...

test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s
+
+---
+
+name:            xor_s1_vcc_vcc_vcc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: xor_s1_vcc_vcc_vcc
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
+    ; WAVE32-LABEL: name: xor_s1_vcc_vcc_vcc
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
+    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = G_CONSTANT i32 0
+    %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
+    %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
+    %5:vcc(s1) = G_XOR %3, %4
+    S_ENDPGM 0, implicit %5
+...
+
+---
+
+name:            xor_s1_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: xor_s1_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    ; WAVE32-LABEL: name: xor_s1_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s1) = G_TRUNC %0
+    %3:sgpr(s1) = G_TRUNC %1
+    %4:sgpr(s1) = G_XOR %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            xor_s1_scc_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: xor_s1_scc_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+    ; WAVE64: [[XOR:%[0-9]+]]:scc(s1) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[XOR]](s1)
+    ; WAVE32-LABEL: name: xor_s1_scc_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
+    ; WAVE32: [[XOR:%[0-9]+]]:scc(s1) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s1)
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s1) = G_TRUNC %0
+    %3:sgpr(s1) = G_TRUNC %1
+    %4:scc(s1) = G_XOR %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            xor_s16_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: xor_s16_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE64: [[XOR:%[0-9]+]]:sgpr(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[XOR]](s16)
+    ; WAVE32-LABEL: name: xor_s16_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+    ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE32: [[XOR:%[0-9]+]]:sgpr(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s16)
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s16) = G_TRUNC %0
+    %3:sgpr(s16) = G_TRUNC %1
+    %4:sgpr(s16) = G_XOR %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            xor_s16_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: xor_s16_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE64: [[XOR:%[0-9]+]]:vgpr(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[XOR]](s16)
+    ; WAVE32-LABEL: name: xor_s16_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
+    ; WAVE32: [[XOR:%[0-9]+]]:vgpr(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s16)
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s16) = G_TRUNC %0
+    %3:vgpr(s16) = G_TRUNC %1
+    %4:vgpr(s16) = G_XOR %2, %3
+    S_ENDPGM 0, implicit %4
+...
+
+---
+
+name:            xor_s32_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: xor_s32_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    ; WAVE32-LABEL: name: xor_s32_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s32) = COPY $sgpr1
+    %2:sgpr(s32) = G_XOR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_s64_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64-LABEL: name: xor_s64_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
+    ; WAVE32-LABEL: name: xor_s64_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE32: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B64_]]
+    %0:sgpr(s64) = COPY $sgpr0_sgpr1
+    %1:sgpr(s64) = COPY $sgpr2_sgpr3
+    %2:sgpr(s64) = G_XOR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_v2s16_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; WAVE64-LABEL: name: xor_v2s16_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0, $sgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    ; WAVE32-LABEL: name: xor_v2s16_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0, $sgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    %0:sgpr(<2 x s16>) = COPY $sgpr0
+    %1:sgpr(<2 x s16>) = COPY $sgpr1
+    %2:sgpr(<2 x s16>) = G_XOR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_v2s32_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64-LABEL: name: xor_v2s32_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
+    ; WAVE32-LABEL: name: xor_v2s32_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE32: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B64_]]
+    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
+    %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
+    %2:sgpr(<2 x s32>) = G_XOR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_v4s16_sgpr_sgpr_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64-LABEL: name: xor_v4s16_sgpr_sgpr_sgpr
+    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
+    ; WAVE32-LABEL: name: xor_v4s16_sgpr_sgpr_sgpr
+    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
+    ; WAVE32: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B64_]]
+    %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+    %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
+    %2:sgpr(<4 x s16>) = G_XOR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_s32_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: xor_s32_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE64: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE64: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
+    ; WAVE32-LABEL: name: xor_s32_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; WAVE32: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = G_XOR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_v2s16_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: xor_v2s16_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+    ; WAVE64: [[XOR:%[0-9]+]]:vgpr(<2 x s16>) = G_XOR [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[XOR]](<2 x s16>)
+    ; WAVE32-LABEL: name: xor_v2s16_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+    ; WAVE32: [[XOR:%[0-9]+]]:vgpr(<2 x s16>) = G_XOR [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[XOR]](<2 x s16>)
+    %0:vgpr(<2 x s16>) = COPY $vgpr0
+    %1:vgpr(<2 x s16>) = COPY $vgpr1
+    %2:vgpr(<2 x s16>) = G_XOR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+
+# This should fail to select
+---
+
+name:            xor_s64_vgpr_vgpr_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; WAVE64-LABEL: name: xor_s64_vgpr_vgpr_vgpr
+    ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+    ; WAVE64: [[XOR:%[0-9]+]]:vgpr(s64) = G_XOR [[COPY]], [[COPY1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[XOR]](s64)
+    ; WAVE32-LABEL: name: xor_s64_vgpr_vgpr_vgpr
+    ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
+    ; WAVE32: [[XOR:%[0-9]+]]:vgpr(s64) = G_XOR [[COPY]], [[COPY1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s64)
+    %0:vgpr(s64) = COPY $vgpr0_vgpr1
+    %1:vgpr(s64) = COPY $vgpr2_vgpr3
+    %2:vgpr(s64) = G_XOR %0, %1
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_s1_vcc_undef_vcc_undef_vcc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    ; WAVE64-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc
+    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 undef %1:sreg_64, undef %2:sreg_64
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
+    ; WAVE32-LABEL: name: xor_s1_vcc_undef_vcc_undef_vcc
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    %2:vcc(s1) = G_XOR undef %0:vcc(s1), undef %1:vcc(s1)
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_s1_sgpr_undef_sgpr_undef_sgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    ; WAVE64-LABEL: name: xor_s1_sgpr_undef_sgpr_undef_sgpr
+    ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    ; WAVE32-LABEL: name: xor_s1_sgpr_undef_sgpr_undef_sgpr
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 undef %1:sreg_32_xm0, undef %2:sreg_32_xm0
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    %2:sgpr(s1) = G_XOR undef %0:sgpr(s1), undef %1:sgpr(s1)
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_s1_vgpr_undef_vgpr_undef_vgpr
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    ; WAVE64-LABEL: name: xor_s1_vgpr_undef_vgpr_undef_vgpr
+    ; WAVE64: [[XOR:%[0-9]+]]:vgpr(s1) = G_XOR undef %1:vgpr, undef %2:vgpr
+    ; WAVE64: S_ENDPGM 0, implicit [[XOR]](s1)
+    ; WAVE32-LABEL: name: xor_s1_vgpr_undef_vgpr_undef_vgpr
+    ; WAVE32: [[XOR:%[0-9]+]]:vgpr(s1) = G_XOR undef %1:vgpr, undef %2:vgpr
+    ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s1)
+    %2:vgpr(s1) = G_XOR undef %0:vgpr(s1), undef %1:vgpr(s1)
+    S_ENDPGM 0, implicit %2
+...
+
+---
+
+name:            xor_s1_vcc_copy_to_vcc
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    ; WAVE64-LABEL: name: xor_s1_vcc_copy_to_vcc
+    ; WAVE64: liveins: $vgpr0, $vgpr1
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
+    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B64_]]
+    ; WAVE32-LABEL: name: xor_s1_vcc_copy_to_vcc
+    ; WAVE32: liveins: $vgpr0, $vgpr1
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY1]], implicit $exec
+    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s1) = G_TRUNC %0
+    %3:vgpr(s1) = G_TRUNC %1
+    %4:vcc(s1) = COPY %2
+    %5:vcc(s1) = COPY %3
+    %6:vcc(s1) = G_XOR %4, %5
+    S_ENDPGM 0, implicit %6
+...
+
+# The selector for the copy of the xor result may constrain the result
+# register of the xor, losing that it is a VCCRegBank context.
+
+# Works for wave32, should fail for wave64
+---
+name:            copy_select_constrain_vcc_result_reg_wave32
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE64: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
+    ; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; WAVE64: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
+    ; WAVE64: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; WAVE64: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
+    ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_64_xexec(s1) = S_XOR_B32 [[COPY1]](s1), [[COPY2]](s1)
+    ; WAVE64: [[COPY3:%[0-9]+]]:sreg_32_xm0(s1) = COPY [[S_XOR_B32_]](s1)
+    ; WAVE64: S_ENDPGM 0, implicit [[COPY3]](s1)
+    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
+    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
+    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
+    %1:vgpr(s32) = COPY $vgpr0
+    %0:vgpr(s1) = G_TRUNC %1(s32)
+    %2:sgpr(s1) = G_CONSTANT i1 true
+    %6:sgpr(s32) = G_CONSTANT i32 0
+    %7:sgpr(p1) = G_IMPLICIT_DEF
+    %9:vcc(s1) = COPY %0(s1)
+    %10:vcc(s1) = COPY %2(s1)
+    %8:vcc(s1) = G_XOR %9, %10
+    %3:sreg_32_xm0(s1) = COPY %8(s1)
+    S_ENDPGM 0, implicit %3
+
+...
+
+# Works for wave64, should fail for wave32
+---
+name:            copy_select_constrain_vcc_result_reg_wave64
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
+    ; WAVE64: liveins: $vgpr0
+    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
+    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec
+    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_MOV_B32_]], implicit $exec
+    ; WAVE64: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]]
+    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B64_]]
+    ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
+    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
+    ; WAVE32: liveins: $vgpr0
+    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
+    ; WAVE32: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
+    ; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; WAVE32: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
+    ; WAVE32: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+    ; WAVE32: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
+    ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_XOR_B32 [[COPY1]](s1), [[COPY2]](s1)
+    ; WAVE32: [[COPY3:%[0-9]+]]:sreg_64_xexec(s1) = COPY [[S_XOR_B32_]](s1)
+    ; WAVE32: S_ENDPGM 0, implicit [[COPY3]](s1)
+    %1:vgpr(s32) = COPY $vgpr0
+    %0:vgpr(s1) = G_TRUNC %1(s32)
+    %2:sgpr(s1) = G_CONSTANT i1 true
+    %6:sgpr(s32) = G_CONSTANT i32 0
+    %7:sgpr(p1) = G_IMPLICIT_DEF
+    %9:vcc(s1) = COPY %0(s1)
+    %10:vcc(s1) = COPY %2(s1)
+    %8:vcc(s1) = G_XOR %9, %10
+    %3:sreg_64_xexec(s1) = COPY %8(s1)
+    S_ENDPGM 0, implicit %3
+
+...