[WIP][RISCV] Use RISCV_32_PCREL reloc for FDE initial location

[edward-jones]

Summary

The default FDE encoding is a 4-byte pc-relative offset, and the standard implementation of MCAsmInfo::getExprForFDESymbol generates a <symbol>-<pc> expression for this (which generates a R_RISCV_ADD32+R_RISCV_SUB32 reloc pair).

For reasons that are still not quite clear, the GNU toolchain generates a R_RISCV_32_PCREL relocation instead of the R_RISCV_ADD32+R_RISCV_SUB32 pair. This patch matches that behavior.

[edward-jones]

Here's a link to the equivalent change made to GAS which should give more context (the commit has since be incorporated into upstream binutils):

https://github.com/riscv/riscv-binutils-gdb/commit/a6cbf936e3dce68114d28cdf60d510a3f78a6d40

I'm leaving this as WIP as I'm missing tests, and I think there's probably a better way to implement this change too (adding the VK_RISCV_PCREL feels like overkill)

[asb]

Thanks Ed. I came to the same conclusion re the need for emitting R_RISCV_32_PCREL when debuggin some issues over the weekend. I had a different fix though - I'll try to compare vs this and get back to you later today.

[luismarques]

@edward-jones Could you please mark this as abandoned, since is has been superseded by D66419?

[edward-jones]

Superceded by D66419

include/llvm/MC/MCExpr.h

enum VariantKind : uint16_t {
     VK_AMDGPU_GOTPCREL32_LO, // symbol@gotpcrel32@lo
     VK_AMDGPU_GOTPCREL32_HI, // symbol@gotpcrel32@hi
     VK_AMDGPU_REL32_LO,      // symbol@rel32@lo
     VK_AMDGPU_REL32_HI,      // symbol@rel32@hi
     VK_AMDGPU_REL64,         // symbol@rel64
     VK_AMDGPU_ABS32_LO,      // symbol@abs32@lo
     VK_AMDGPU_ABS32_HI,      // symbol@abs32@hi
 
+    VK_RISCV_PCREL,
+
     VK_TPREL,
     VK_DTPREL
   };
 
 private:
   /// The symbol reference modifier.
   const VariantKind Kind;
 

lib/MC/MCExpr.cpp

StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
   case VK_WASM_TBREL: return "TBREL";
   case VK_AMDGPU_GOTPCREL32_LO: return "gotpcrel32@lo";
   case VK_AMDGPU_GOTPCREL32_HI: return "gotpcrel32@hi";
   case VK_AMDGPU_REL32_LO: return "rel32@lo";
   case VK_AMDGPU_REL32_HI: return "rel32@hi";
   case VK_AMDGPU_REL64: return "rel64";
   case VK_AMDGPU_ABS32_LO: return "abs32@lo";
   case VK_AMDGPU_ABS32_HI: return "abs32@hi";
+  case VK_RISCV_PCREL: return "pcrel";
   }
   llvm_unreachable("Invalid variant kind");
 }
 
 MCSymbolRefExpr::VariantKind
 MCSymbolRefExpr::getVariantKindForName(StringRef Name) {
   return StringSwitch<VariantKind>(Name.lower())
     .Case("dtprel", VK_DTPREL)

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

 //===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/RISCVFixupKinds.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCValue.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
 namespace {
 class RISCVELFObjectWriter : public MCELFObjectTargetWriter {
 public:

 
 RISCVELFObjectWriter::~RISCVELFObjectWriter() {}
 
 unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
                                             const MCValue &Target,
                                             const MCFixup &Fixup,
                                             bool IsPCRel) const {
   // Determine the type of the relocation
+  MCSymbolRefExpr::VariantKind Variant = Target.getAccessVariant();
   switch ((unsigned)Fixup.getKind()) {
   default:
     llvm_unreachable("invalid fixup kind!");
   case FK_Data_4:
+    if (Variant == MCSymbolRefExpr::VK_RISCV_PCREL)
+      return ELF::R_RISCV_32_PCREL;
+    else
       return ELF::R_RISCV_32;
   case FK_Data_8:
     return ELF::R_RISCV_64;
   case FK_Data_Add_1:
     return ELF::R_RISCV_ADD8;
   case FK_Data_Add_2:
     return ELF::R_RISCV_ADD16;
   case FK_Data_Add_4:
     return ELF::R_RISCV_ADD32;

lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h

 namespace llvm {
 class Triple;
 
 class RISCVMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
   explicit RISCVMCAsmInfo(const Triple &TargetTriple);
+
+  const MCExpr* getExprForFDESymbol(const MCSymbol *Sym,
+                                    unsigned Encoding,
+                                    MCStreamer &Streamer) const override;
 };
 
 } // namespace llvm
 
 #endif

lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp

 //===-- RISCVMCAsmInfo.cpp - RISCV Asm properties -------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the RISCVMCAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVMCAsmInfo.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/BinaryFormat/Dwarf.h"
+#include "llvm/MC/MCStreamer.h"
 using namespace llvm;
 
 void RISCVMCAsmInfo::anchor() {}
 
 RISCVMCAsmInfo::RISCVMCAsmInfo(const Triple &TT) {
   CodePointerSize = CalleeSaveStackSlotSize = TT.isArch64Bit() ? 8 : 4;
   CommentString = "#";
   AlignmentIsInBytes = false;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
   Data16bitsDirective = "\t.half\t";
   Data32bitsDirective = "\t.word\t";
 }
+
+const MCExpr*
+RISCVMCAsmInfo::getExprForFDESymbol(const MCSymbol *Sym,
+                                    unsigned Encoding,
+                                    MCStreamer &Streamer) const {
+  auto &Ctx = Streamer.getContext();
+  if (Encoding | dwarf::DW_EH_PE_pcrel)
+    return MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_RISCV_PCREL, Ctx);
+  else
+    return MCSymbolRefExpr::create(Sym, Ctx);
+}