[mips] Fix JmpLink to texternalsym and tglobaladdr on mcroMIPS R6

[atanasyan]

Summary

There is not match for the MipsJmpLink texternalsym and MipsJmpLink tglobaladdr patterns for microMIPS R6. As a result LLVM incorrectly selects the JALRC16 compact 2-byte instruction which takes a target instruction address from a register only and assign R_MIPS_32 relocation for this instruction. This relocation completely overwrites JALRC16 and nearby instructions.

This patch adds missed matching patterns, selects BALC instruction and assign a correct R_MICROMIPS_PC26_S1 relocation.

[Petar.Avramovic]

LGTM.

llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

 def : MipsPat<(not GPR32:$in),
               (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
 // Patterns for load with a reg+imm operand.
 let AddedComplexity = 41 in {
   def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
   def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
 }
 
+let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in {
+  class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> :
+    PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>,
+    PseudoInstExpansion<(JumpInst Opnd:$target)>;
+}
+
+def JAL_MMR6 : JumpLinkMMR6<BALC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
+
+def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
+              (JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
+def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)),
+              (JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
+
 def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
 
 def TAILCALLREG_MMR6  : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
 
 def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
                                                          GPR32Opnd>,
                                 ISA_MICROMIPS32R6;
 

llvm/lib/Target/Mips/MipsScheduleGeneric.td

 
 def : InstRW<[GenericWriteJump], (instrs BC16_MMR6, BC1EQZC_MMR6, BC1NEZC_MMR6,
                                   BC2EQZC_MMR6, BC2NEZC_MMR6, BC_MMR6,
                                   BEQC_MMR6, BEQZC16_MMR6, BEQZC_MMR6,
                                   BGEC_MMR6, BGEUC_MMR6, BGEZC_MMR6,
                                   BGTZC_MMR6, BLEZC_MMR6, BLTC_MMR6,
                                   BLTUC_MMR6, BLTZC_MMR6, BNEC_MMR6,
                                   BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6,
-                                  BOVC_MMR6, DERET_MMR6, ERETNC_MMR6,
+                                  BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, JAL_MMR6,
                                   ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM,
                                   JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6,
                                   B_MMR6_Pseudo, PseudoIndirectBranch_MMR6)>;
 
 def : InstRW<[GenericWriteJumpAndLink], (instrs BALC_MMR6, BEQZALC_MMR6,
                                          BGEZALC_MMR6, BGTZALC_MMR6,
                                          BLEZALC_MMR6, BLTZALC_MMR6,
                                          BNEZALC_MMR6, JALRC16_MMR6,

llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll

 ; MMR6-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR6-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR6-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    .cfi_offset 31, -4
-; MMR6-SF-NEXT:    jalr __fixsfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
+; MMR6-SF-NEXT:    balc __fixsfsi # <MCInst #{{[0-9]+}} BALC_MMR6
 ; MMR6-SF-NEXT:    # <MCOperand Expr:(__fixsfsi)>>
 ; MMR6-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>

 ; MMR6-SF-NEXT:    # <MCOperand Imm:-24>>
 ; MMR6-SF-NEXT:    .cfi_def_cfa_offset 24
 ; MMR6-SF-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} SW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    .cfi_offset 31, -4
-; MMR6-SF-NEXT:    jalr __fixdfsi # <MCInst #{{[0-9]+}} JALRC16_MMR6
+; MMR6-SF-NEXT:    balc __fixdfsi # <MCInst #{{[0-9]+}} BALC_MMR6
 ; MMR6-SF-NEXT:    # <MCOperand Expr:(__fixdfsi)>>
 ; MMR6-SF-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
 ; MMR6-SF-NEXT:    # <MCInst #{{[0-9]+}} LW
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:20>>
 ; MMR6-SF-NEXT:    addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
 ; MMR6-SF-NEXT:    # <MCOperand Imm:24>>
 ; MMR6-SF-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
 ; MMR6-SF-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
 entry:
   %conv = fptosi double %t to i32
   ret i32 %conv
 }

llvm/test/CodeGen/Mips/micromips-delay-slot.ll

entry:
   %call = call i32 @bar(i32 signext %shl)
   ret i32 %call
 }
 
 declare i32 @bar(i32 signext) #1
 
 ; CHECK:      jals
 ; CHECK-NEXT: sll16
-; CHECK-MMR6: jal
+; CHECK-MMR6: balc
 ; CHECK-MMR6-NOT: sll16

llvm/test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll

-; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=finalize-isel < %s | FileCheck %s
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips \
+; RUN:     -stop-after=finalize-isel < %s | FileCheck --check-prefix=MM2 %s
+; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r6 -mattr=+micromips \
+; RUN:     -stop-after=finalize-isel < %s | FileCheck --check-prefix=MM6 %s
 
-; CHECK: JAL_MM
-; CHECK-NOT: JALR16_MM
+; MM2: JAL_MM @bar
+; MM2: JAL_MM &memset
+; MM2-NOT: JALR16_MM
+
+; MM6: JAL_MMR6 @bar
+; MM6: JAL_MMR6 &memset
+; MM6-NOT: JALRC16_MMR6
 
 define dso_local void @foo(i32* nocapture %ar) local_unnamed_addr {
 entry:
+  call void @bar()
   %0 = bitcast i32* %ar to i8*
   tail call void @llvm.memset.p0i8.i32(i8* align 4 %0, i8 0, i32 100, i1 false)
   ret void
 }
 
 declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1)
+declare void @bar()

llvm/test/CodeGen/Mips/tailcall/tailcall.ll

 
 define i32 @caller1(i32 %a0) nounwind {
 entry:
 ; ALL-LABEL: caller1:
 ; PIC32: jalr $25
 ; PIC32MM: jalr $25
 ; PIC32R6: jalr $25
 ; STATIC32: jal
-; STATIC32MMR6: jal
+; STATIC32MMR6: balc
 ; N64: jalr $25
 ; N64R6: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee1(i32 1, i32 1, i32 1, i32 %a0) nounwind
   ret i32 %call
 }
 
 declare i32 @callee1(i32, i32, i32, i32)
 
 define i32 @caller2(i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind {
 entry:
 ; ALL-LABEL: caller2
 ; PIC32: jalr $25
 ; PIC32MM: jalr $25
 ; PIC32R6: jalr $25
 ; STATIC32: jal
-; STATIC32MMR6: jal
+; STATIC32MMR6: balc
 ; N64: jalr $25
 ; N64R6: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee2(i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind
   ret i32 %call
 }
 
 declare i32 @callee2(i32, i32, i32, i32, i32)
 
 define i32 @caller3(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) nounwind {
 entry:
 ; ALL-LABEL: caller3:
 ; PIC32: jalr $25
 ; PIC32R6: jalr $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
-; STATIC32MMR6: jal
+; STATIC32MMR6: balc
 ; N64: jalr $25
 ; N64R6: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee3(i32 1, i32 1, i32 1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) nounwind
   ret i32 %call
 }
 

 
 define internal fastcc i32 @caller8_1() nounwind noinline {
 entry:
 ; ALL-LABEL: caller8_1:
 ; PIC32: jalr $25
 ; PIC32R6: jalr $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
-; STATIC32MMR6: jal
+; STATIC32MMR6: balc
 ; PIC64: jalr $25
 ; STATIC64: jal
 ; PIC16: jalrc
 
   %call = tail call i32 (i32, ...) @callee8(i32 2, i32 1) nounwind
   ret i32 %call
 }
 

 
 define internal fastcc i32 @caller9_1() nounwind noinline {
 entry:
 ; ALL-LABEL: caller9_1:
 ; PIC32: jalr $25
 ; PIC32R6: jalrc $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
-; STATIC32MMR6: jal
+; STATIC32MMR6: balc
 ; STATIC64: jal
 ; PIC64: jalr $25
 ; PIC64R6: jalrc $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee9(%struct.S* byval @gs1) nounwind
   ret i32 %call
 }
 
 declare i32 @callee10(i32, i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @caller10(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) nounwind {
 entry:
 ; ALL-LABEL: caller10:
 ; PIC32: jalr $25
 ; PIC32R6: jalr $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
-; STATIC32MMR6: jal
+; STATIC32MMR6: balc
 ; STATIC64: jal
 ; PIC64: jalr $25
 ; PIC64R6: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee10(i32 %a8, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind
   ret i32 %call
 }
 
 declare i32 @callee11(%struct.S* byval)
 
 define i32 @caller11() nounwind noinline {
 entry:
 ; ALL-LABEL: caller11:
 ; PIC32: jalr $25
 ; PIC32R6: jalrc $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
-; STATIC32MMR6: jal
+; STATIC32MMR6: balc
 ; STATIC64: jal
 ; PIC64: jalr $25
 ; PIC64R6: jalrc $25
 ; PIC16: jalrc
 
   %call = tail call i32 @callee11(%struct.S* byval @gs1) nounwind
   ret i32 %call
 }
 
 declare i32 @callee12()
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
 
 define i32 @caller12(%struct.S* nocapture byval %a0) nounwind {
 entry:
 ; ALL-LABEL: caller12:
 ; PIC32: jalr $25
 ; PIC32R6: jalrc $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
-; STATIC32MMR6: jal
+; STATIC32MMR6: balc
 ; STATIC64: jal
 ; PIC64: jalr $25
 ; PIC64R6: jalrc $25
 ; PIC16: jalrc
 
   %0 = bitcast %struct.S* %a0 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 bitcast (%struct.S* @gs1 to i8*), i8* align 4 %0, i32 8, i1 false)
   %call = tail call i32 @callee12() nounwind
   ret i32 %call
 }
 
 declare i32 @callee13(i32, ...)
 
 define i32 @caller13() nounwind {
 entry:
 ; ALL-LABEL: caller13:
 ; PIC32: jalr $25
 ; PIC32R6: jalr $25
 ; PIC32MM: jalr $25
 ; STATIC32: jal
-; STATIC32MMR6: jal
+; STATIC32MMR6: balc
 ; STATIC64: jal
 ; PIC64R6: jalr $25
 ; PIC64: jalr $25
 ; PIC16: jalrc
 
   %call = tail call i32 (i32, ...) @callee13(i32 1, i32 2) nounwind
   ret i32 %call
 }