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Differential D64502

[ARM] Remove nonexistent unsigned forms of MVE VQDMLAH.
ClosedPublic

Authored by simon_tatham on Jul 10 2019, 8:18 AM.

Details

Reviewers
miyuki
Commits
rG7916198a4105: [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH.
rL365747: [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH.
Summary

The VQDMLAH.U8, VQDMLAH.U16 and VQDMLAH.U32 instructions don't
actually exist: the Armv8.1-M architecture spec only lists signed
forms of that instruction. The unsigned ones were added in error: they
existed in an early draft of the spec, but they were removed before
the public version, and we missed that particular spec change.

Also affects the variant forms VQDMLASH, VQRDMLAH and VQRDMLASH.

Diff Detail

Event Timeline

simon_tatham created this revision.Jul 10 2019, 8:18 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 10 2019, 8:18 AM
Herald added subscribers: llvm-commits, dmgreen, hiraditya and 2 others. · View Herald Transcript
Harbormaster completed remote builds in B34698: Diff 208971.Jul 10 2019, 8:19 AM
miyuki accepted this revision.Jul 10 2019, 8:24 AM
This revision is now accepted and ready to land.Jul 10 2019, 8:24 AM
Closed by commit rL365747: [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH. (authored by statham). · Explain WhyJul 11 2019, 2:53 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
3 lines
test/
MC/
ARM/
48 lines
Disassembler/
ARM/
27 lines

Diff 208971

llvm/lib/Target/ARM/ARMInstrMVE.td

Show First 20 Lines • Show All 3,349 Lines • ▼ Show 20 Linesclass MVE_VQDMLAH_qr<string iname, string suffix, bit U, bits<2> size,
let Inst{8} = 0b0; let Inst{8} = 0b0;
let Inst{5} = bit_5; let Inst{5} = bit_5;
} }
multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> { multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> {
def s8 : MVE_VQDMLAH_qr<iname, "s8", 0b0, 0b00, bit_5, bit_12>; def s8 : MVE_VQDMLAH_qr<iname, "s8", 0b0, 0b00, bit_5, bit_12>;
def s16 : MVE_VQDMLAH_qr<iname, "s16", 0b0, 0b01, bit_5, bit_12>; def s16 : MVE_VQDMLAH_qr<iname, "s16", 0b0, 0b01, bit_5, bit_12>;
def s32 : MVE_VQDMLAH_qr<iname, "s32", 0b0, 0b10, bit_5, bit_12>; def s32 : MVE_VQDMLAH_qr<iname, "s32", 0b0, 0b10, bit_5, bit_12>;
def u8 : MVE_VQDMLAH_qr<iname, "u8", 0b1, 0b00, bit_5, bit_12>;
def u16 : MVE_VQDMLAH_qr<iname, "u16", 0b1, 0b01, bit_5, bit_12>;
def u32 : MVE_VQDMLAH_qr<iname, "u32", 0b1, 0b10, bit_5, bit_12>;
} }
defm MVE_VQDMLAH_qr : MVE_VQDMLAH_qr_types<"vqdmlah", 0b1, 0b0>; defm MVE_VQDMLAH_qr : MVE_VQDMLAH_qr_types<"vqdmlah", 0b1, 0b0>;
defm MVE_VQRDMLAH_qr : MVE_VQDMLAH_qr_types<"vqrdmlah", 0b0, 0b0>; defm MVE_VQRDMLAH_qr : MVE_VQDMLAH_qr_types<"vqrdmlah", 0b0, 0b0>;
defm MVE_VQDMLASH_qr : MVE_VQDMLAH_qr_types<"vqdmlash", 0b1, 0b1>; defm MVE_VQDMLASH_qr : MVE_VQDMLAH_qr_types<"vqdmlash", 0b1, 0b1>;
defm MVE_VQRDMLASH_qr : MVE_VQDMLAH_qr_types<"vqrdmlash", 0b0, 0b1>; defm MVE_VQRDMLASH_qr : MVE_VQDMLAH_qr_types<"vqrdmlash", 0b0, 0b1>;
class MVE_VxDUP<string iname, string suffix, bits<2> size, bit bit_12, class MVE_VxDUP<string iname, string suffix, bits<2> size, bit bit_12,
▲ Show 20 Lines • Show All 1,055 Lines • Show Last 20 Lines

llvm/test/MC/ARM/mve-qdest-rsrc.s

Show First 20 Lines • Show All 378 Lines • ▼ Show 20 Lines
# CHECK: vqdmlash.s16 q0, q5, lr @ encoding: [0x1a,0xee,0x6e,0x1e] # CHECK: vqdmlash.s16 q0, q5, lr @ encoding: [0x1a,0xee,0x6e,0x1e]
# CHECK-NOFP: vqdmlash.s16 q0, q5, lr @ encoding: [0x1a,0xee,0x6e,0x1e] # CHECK-NOFP: vqdmlash.s16 q0, q5, lr @ encoding: [0x1a,0xee,0x6e,0x1e]
vqdmlash.s16 q0, q5, lr vqdmlash.s16 q0, q5, lr
# CHECK: vqdmlash.s32 q0, q2, r3 @ encoding: [0x24,0xee,0x63,0x1e] # CHECK: vqdmlash.s32 q0, q2, r3 @ encoding: [0x24,0xee,0x63,0x1e]
# CHECK-NOFP: vqdmlash.s32 q0, q2, r3 @ encoding: [0x24,0xee,0x63,0x1e] # CHECK-NOFP: vqdmlash.s32 q0, q2, r3 @ encoding: [0x24,0xee,0x63,0x1e]
vqdmlash.s32 q0, q2, r3 vqdmlash.s32 q0, q2, r3
# CHECK: vqdmlash.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x62,0x1e] # ERROR: [[@LINE+2]]:9: error: invalid operand for instruction
# CHECK-NOFP: vqdmlash.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x62,0x1e] # ERROR-NOFP: [[@LINE+1]]:9: error: invalid operand for instruction
vqdmlash.u8 q0, q4, r2 vqdmlash.u8 q0, q4, r2
# CHECK: vqdmlash.u16 q1, q4, r2 @ encoding: [0x18,0xfe,0x62,0x3e] # ERROR: [[@LINE+2]]:9: error: invalid operand for instruction
# CHECK-NOFP: vqdmlash.u16 q1, q4, r2 @ encoding: [0x18,0xfe,0x62,0x3e] # ERROR-NOFP: [[@LINE+1]]:9: error: invalid operand for instruction
vqdmlash.u16 q1, q4, r2 vqdmlash.u16 q1, q4, r2
# CHECK: vqdmlash.u32 q1, q5, r0 @ encoding: [0x2a,0xfe,0x60,0x3e] # ERROR: [[@LINE+2]]:9: error: invalid operand for instruction
# CHECK-NOFP: vqdmlash.u32 q1, q5, r0 @ encoding: [0x2a,0xfe,0x60,0x3e] # ERROR-NOFP: [[@LINE+1]]:9: error: invalid operand for instruction
vqdmlash.u32 q1, q5, r0 vqdmlash.u32 q1, q5, r0
# CHECK: vqdmlah.s8 q0, q3, r3 @ encoding: [0x06,0xee,0x63,0x0e] # CHECK: vqdmlah.s8 q0, q3, r3 @ encoding: [0x06,0xee,0x63,0x0e]
# CHECK-NOFP: vqdmlah.s8 q0, q3, r3 @ encoding: [0x06,0xee,0x63,0x0e] # CHECK-NOFP: vqdmlah.s8 q0, q3, r3 @ encoding: [0x06,0xee,0x63,0x0e]
vqdmlah.s8 q0, q3, r3 vqdmlah.s8 q0, q3, r3
# CHECK: vqdmlah.s16 q5, q3, r9 @ encoding: [0x16,0xee,0x69,0xae] # CHECK: vqdmlah.s16 q5, q3, r9 @ encoding: [0x16,0xee,0x69,0xae]
# CHECK-NOFP: vqdmlah.s16 q5, q3, r9 @ encoding: [0x16,0xee,0x69,0xae] # CHECK-NOFP: vqdmlah.s16 q5, q3, r9 @ encoding: [0x16,0xee,0x69,0xae]
vqdmlah.s16 q5, q3, r9 vqdmlah.s16 q5, q3, r9
# CHECK: vqdmlah.s32 q0, q1, r11 @ encoding: [0x22,0xee,0x6b,0x0e] # CHECK: vqdmlah.s32 q0, q1, r11 @ encoding: [0x22,0xee,0x6b,0x0e]
# CHECK-NOFP: vqdmlah.s32 q0, q1, r11 @ encoding: [0x22,0xee,0x6b,0x0e] # CHECK-NOFP: vqdmlah.s32 q0, q1, r11 @ encoding: [0x22,0xee,0x6b,0x0e]
vqdmlah.s32 q0, q1, r11 vqdmlah.s32 q0, q1, r11
# CHECK: vqdmlah.u8 q0, q2, lr @ encoding: [0x04,0xfe,0x6e,0x0e] # ERROR: [[@LINE+2]]:8: error: invalid operand for instruction
# CHECK-NOFP: vqdmlah.u8 q0, q2, lr @ encoding: [0x04,0xfe,0x6e,0x0e] # ERROR-NOFP: [[@LINE+1]]:8: error: invalid operand for instruction
vqdmlah.u8 q0, q2, lr vqdmlah.u8 q0, q2, lr
# CHECK: vqdmlah.u16 q0, q3, r10 @ encoding: [0x16,0xfe,0x6a,0x0e] # ERROR: [[@LINE+2]]:8: error: invalid operand for instruction
# CHECK-NOFP: vqdmlah.u16 q0, q3, r10 @ encoding: [0x16,0xfe,0x6a,0x0e] # ERROR-NOFP: [[@LINE+1]]:8: error: invalid operand for instruction
vqdmlah.u16 q0, q3, r10 vqdmlah.u16 q0, q3, r10
# CHECK: vqdmlah.u32 q1, q5, r2 @ encoding: [0x2a,0xfe,0x62,0x2e] # ERROR: [[@LINE+2]]:8: error: invalid operand for instruction
# CHECK-NOFP: vqdmlah.u32 q1, q5, r2 @ encoding: [0x2a,0xfe,0x62,0x2e] # ERROR-NOFP: [[@LINE+1]]:8: error: invalid operand for instruction
vqdmlah.u32 q1, q5, r2 vqdmlah.u32 q1, q5, r2
# CHECK: vqrdmlash.s8 q0, q5, r10 @ encoding: [0x0a,0xee,0x4a,0x1e] # CHECK: vqrdmlash.s8 q0, q5, r10 @ encoding: [0x0a,0xee,0x4a,0x1e]
# CHECK-NOFP: vqrdmlash.s8 q0, q5, r10 @ encoding: [0x0a,0xee,0x4a,0x1e] # CHECK-NOFP: vqrdmlash.s8 q0, q5, r10 @ encoding: [0x0a,0xee,0x4a,0x1e]
vqrdmlash.s8 q0, q5, r10 vqrdmlash.s8 q0, q5, r10
# CHECK: vqrdmlash.s16 q0, q3, r2 @ encoding: [0x16,0xee,0x42,0x1e] # CHECK: vqrdmlash.s16 q0, q3, r2 @ encoding: [0x16,0xee,0x42,0x1e]
# CHECK-NOFP: vqrdmlash.s16 q0, q3, r2 @ encoding: [0x16,0xee,0x42,0x1e] # CHECK-NOFP: vqrdmlash.s16 q0, q3, r2 @ encoding: [0x16,0xee,0x42,0x1e]
vqrdmlash.s16 q0, q3, r2 vqrdmlash.s16 q0, q3, r2
# CHECK: vqrdmlash.s32 q0, q0, r4 @ encoding: [0x20,0xee,0x44,0x1e] # CHECK: vqrdmlash.s32 q0, q0, r4 @ encoding: [0x20,0xee,0x44,0x1e]
# CHECK-NOFP: vqrdmlash.s32 q0, q0, r4 @ encoding: [0x20,0xee,0x44,0x1e] # CHECK-NOFP: vqrdmlash.s32 q0, q0, r4 @ encoding: [0x20,0xee,0x44,0x1e]
vqrdmlash.s32 q0, q0, r4 vqrdmlash.s32 q0, q0, r4
# CHECK: vqrdmlash.u8 q0, q4, r9 @ encoding: [0x08,0xfe,0x49,0x1e] # ERROR: [[@LINE+2]]:10: error: invalid operand for instruction
# CHECK-NOFP: vqrdmlash.u8 q0, q4, r9 @ encoding: [0x08,0xfe,0x49,0x1e] # ERROR-NOFP: [[@LINE+1]]:10: error: invalid operand for instruction
vqrdmlash.u8 q0, q4, r9 vqrdmlash.u8 q0, q4, r9
# CHECK: vqrdmlash.u16 q0, q6, r12 @ encoding: [0x1c,0xfe,0x4c,0x1e] # ERROR: [[@LINE+2]]:10: error: invalid operand for instruction
# CHECK-NOFP: vqrdmlash.u16 q0, q6, r12 @ encoding: [0x1c,0xfe,0x4c,0x1e] # ERROR-NOFP: [[@LINE+1]]:10: error: invalid operand for instruction
vqrdmlash.u16 q0, q6, r12 vqrdmlash.u16 q0, q6, r12
# CHECK: vqrdmlash.u32 q0, q3, r7 @ encoding: [0x26,0xfe,0x47,0x1e] # ERROR: [[@LINE+2]]:10: error: invalid operand for instruction
# CHECK-NOFP: vqrdmlash.u32 q0, q3, r7 @ encoding: [0x26,0xfe,0x47,0x1e] # ERROR-NOFP: [[@LINE+1]]:10: error: invalid operand for instruction
vqrdmlash.u32 q0, q3, r7 vqrdmlash.u32 q0, q3, r7
# CHECK: vqrdmlah.s8 q0, q5, r11 @ encoding: [0x0a,0xee,0x4b,0x0e] # CHECK: vqrdmlah.s8 q0, q5, r11 @ encoding: [0x0a,0xee,0x4b,0x0e]
# CHECK-NOFP: vqrdmlah.s8 q0, q5, r11 @ encoding: [0x0a,0xee,0x4b,0x0e] # CHECK-NOFP: vqrdmlah.s8 q0, q5, r11 @ encoding: [0x0a,0xee,0x4b,0x0e]
vqrdmlah.s8 q0, q5, r11 vqrdmlah.s8 q0, q5, r11
# CHECK: vqrdmlah.s16 q0, q2, r10 @ encoding: [0x14,0xee,0x4a,0x0e] # CHECK: vqrdmlah.s16 q0, q2, r10 @ encoding: [0x14,0xee,0x4a,0x0e]
# CHECK-NOFP: vqrdmlah.s16 q0, q2, r10 @ encoding: [0x14,0xee,0x4a,0x0e] # CHECK-NOFP: vqrdmlah.s16 q0, q2, r10 @ encoding: [0x14,0xee,0x4a,0x0e]
vqrdmlah.s16 q0, q2, r10 vqrdmlah.s16 q0, q2, r10
# CHECK: vqrdmlah.s32 q0, q4, r11 @ encoding: [0x28,0xee,0x4b,0x0e] # CHECK: vqrdmlah.s32 q0, q4, r11 @ encoding: [0x28,0xee,0x4b,0x0e]
# CHECK-NOFP: vqrdmlah.s32 q0, q4, r11 @ encoding: [0x28,0xee,0x4b,0x0e] # CHECK-NOFP: vqrdmlah.s32 q0, q4, r11 @ encoding: [0x28,0xee,0x4b,0x0e]
vqrdmlah.s32 q0, q4, r11 vqrdmlah.s32 q0, q4, r11
# CHECK: vqrdmlah.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x42,0x0e] # ERROR: [[@LINE+2]]:9: error: invalid operand for instruction
# CHECK-NOFP: vqrdmlah.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x42,0x0e] # ERROR-NOFP: [[@LINE+1]]:9: error: invalid operand for instruction
vqrdmlah.u8 q0, q4, r2 vqrdmlah.u8 q0, q4, r2
# CHECK: vqrdmlah.u16 q0, q6, r1 @ encoding: [0x1c,0xfe,0x41,0x0e] # ERROR: [[@LINE+2]]:9: error: invalid operand for instruction
# CHECK-NOFP: vqrdmlah.u16 q0, q6, r1 @ encoding: [0x1c,0xfe,0x41,0x0e] # ERROR-NOFP: [[@LINE+1]]:9: error: invalid operand for instruction
vqrdmlah.u16 q0, q6, r1 vqrdmlah.u16 q0, q6, r1
# CHECK: vqrdmlah.u32 q0, q4, r2 @ encoding: [0x28,0xfe,0x42,0x0e] # ERROR: [[@LINE+2]]:9: error: invalid operand for instruction
# CHECK-NOFP: vqrdmlah.u32 q0, q4, r2 @ encoding: [0x28,0xfe,0x42,0x0e] # ERROR-NOFP: [[@LINE+1]]:9: error: invalid operand for instruction
vqrdmlah.u32 q0, q4, r2 vqrdmlah.u32 q0, q4, r2
# CHECK: viwdup.u8 q0, lr, r1, #1 @ encoding: [0x0f,0xee,0x60,0x0f] # CHECK: viwdup.u8 q0, lr, r1, #1 @ encoding: [0x0f,0xee,0x60,0x0f]
# CHECK-NOFP: viwdup.u8 q0, lr, r1, #1 @ encoding: [0x0f,0xee,0x60,0x0f] # CHECK-NOFP: viwdup.u8 q0, lr, r1, #1 @ encoding: [0x0f,0xee,0x60,0x0f]
viwdup.u8 q0, lr, r1, #1 viwdup.u8 q0, lr, r1, #1
# CHECK: viwdup.u16 q1, r10, r1, #8 @ encoding: [0x1b,0xee,0xe1,0x2f] # CHECK: viwdup.u16 q1, r10, r1, #8 @ encoding: [0x1b,0xee,0xe1,0x2f]
# CHECK-NOFP: viwdup.u16 q1, r10, r1, #8 @ encoding: [0x1b,0xee,0xe1,0x2f] # CHECK-NOFP: viwdup.u16 q1, r10, r1, #8 @ encoding: [0x1b,0xee,0xe1,0x2f]
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llvm/test/MC/Disassembler/ARM/mve-qdest-rsrc.txt

# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2>%t | FileCheck %s
# RUN: FileCheck --check-prefix=ERROR < %t %s
# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
# CHECK: vsub.i8 q0, q3, r3 @ encoding: [0x07,0xee,0x43,0x1f] # CHECK: vsub.i8 q0, q3, r3 @ encoding: [0x07,0xee,0x43,0x1f]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x07,0xee,0x43,0x1f] [0x07,0xee,0x43,0x1f]
# CHECK: vsub.i16 q0, q7, lr @ encoding: [0x1f,0xee,0x4e,0x1f] # CHECK: vsub.i16 q0, q7, lr @ encoding: [0x1f,0xee,0x4e,0x1f]
▲ Show 20 Lines • Show All 367 Lines • ▼ Show 20 Lines
# CHECK: vqdmlash.s16 q0, q5, lr @ encoding: [0x1a,0xee,0x6e,0x1e] # CHECK: vqdmlash.s16 q0, q5, lr @ encoding: [0x1a,0xee,0x6e,0x1e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x1a,0xee,0x6e,0x1e] [0x1a,0xee,0x6e,0x1e]
# CHECK: vqdmlash.s32 q0, q2, r3 @ encoding: [0x24,0xee,0x63,0x1e] # CHECK: vqdmlash.s32 q0, q2, r3 @ encoding: [0x24,0xee,0x63,0x1e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x24,0xee,0x63,0x1e] [0x24,0xee,0x63,0x1e]
# CHECK: vqdmlash.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x62,0x1e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x08,0xfe,0x62,0x1e] [0x08,0xfe,0x62,0x1e]
# CHECK: vqdmlash.u16 q1, q4, r2 @ encoding: [0x18,0xfe,0x62,0x3e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x18,0xfe,0x62,0x3e] [0x18,0xfe,0x62,0x3e]
# CHECK: vqdmlash.u32 q1, q5, r0 @ encoding: [0x2a,0xfe,0x60,0x3e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x2a,0xfe,0x60,0x3e] [0x2a,0xfe,0x60,0x3e]
# CHECK: vqdmlah.s8 q0, q3, r3 @ encoding: [0x06,0xee,0x63,0x0e] # CHECK: vqdmlah.s8 q0, q3, r3 @ encoding: [0x06,0xee,0x63,0x0e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x06,0xee,0x63,0x0e] [0x06,0xee,0x63,0x0e]
# CHECK: vqdmlah.s16 q5, q3, r9 @ encoding: [0x16,0xee,0x69,0xae] # CHECK: vqdmlah.s16 q5, q3, r9 @ encoding: [0x16,0xee,0x69,0xae]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x16,0xee,0x69,0xae] [0x16,0xee,0x69,0xae]
# CHECK: vqdmlah.s32 q0, q1, r11 @ encoding: [0x22,0xee,0x6b,0x0e] # CHECK: vqdmlah.s32 q0, q1, r11 @ encoding: [0x22,0xee,0x6b,0x0e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x22,0xee,0x6b,0x0e] [0x22,0xee,0x6b,0x0e]
# CHECK: vqdmlah.u8 q0, q2, lr @ encoding: [0x04,0xfe,0x6e,0x0e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x04,0xfe,0x6e,0x0e] [0x04,0xfe,0x6e,0x0e]
# CHECK: vqdmlah.u16 q0, q3, r10 @ encoding: [0x16,0xfe,0x6a,0x0e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x16,0xfe,0x6a,0x0e] [0x16,0xfe,0x6a,0x0e]
# CHECK: vqdmlah.u32 q1, q5, r2 @ encoding: [0x2a,0xfe,0x62,0x2e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x2a,0xfe,0x62,0x2e] [0x2a,0xfe,0x62,0x2e]
# CHECK: vqrdmlash.s8 q0, q5, r10 @ encoding: [0x0a,0xee,0x4a,0x1e] # CHECK: vqrdmlash.s8 q0, q5, r10 @ encoding: [0x0a,0xee,0x4a,0x1e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x0a,0xee,0x4a,0x1e] [0x0a,0xee,0x4a,0x1e]
# CHECK: vqrdmlash.s16 q0, q3, r2 @ encoding: [0x16,0xee,0x42,0x1e] # CHECK: vqrdmlash.s16 q0, q3, r2 @ encoding: [0x16,0xee,0x42,0x1e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x16,0xee,0x42,0x1e] [0x16,0xee,0x42,0x1e]
# CHECK: vqrdmlash.s32 q0, q0, r4 @ encoding: [0x20,0xee,0x44,0x1e] # CHECK: vqrdmlash.s32 q0, q0, r4 @ encoding: [0x20,0xee,0x44,0x1e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x20,0xee,0x44,0x1e] [0x20,0xee,0x44,0x1e]
# CHECK: vqrdmlash.u8 q0, q4, r9 @ encoding: [0x08,0xfe,0x49,0x1e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x08,0xfe,0x49,0x1e] [0x08,0xfe,0x49,0x1e]
# CHECK: vqrdmlash.u16 q0, q6, r12 @ encoding: [0x1c,0xfe,0x4c,0x1e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x1c,0xfe,0x4c,0x1e] [0x1c,0xfe,0x4c,0x1e]
# CHECK: vqrdmlash.u32 q0, q3, r7 @ encoding: [0x26,0xfe,0x47,0x1e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x26,0xfe,0x47,0x1e] [0x26,0xfe,0x47,0x1e]
# CHECK: vqrdmlah.s8 q0, q5, r11 @ encoding: [0x0a,0xee,0x4b,0x0e] # CHECK: vqrdmlah.s8 q0, q5, r11 @ encoding: [0x0a,0xee,0x4b,0x0e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x0a,0xee,0x4b,0x0e] [0x0a,0xee,0x4b,0x0e]
# CHECK: vqrdmlah.s16 q0, q2, r10 @ encoding: [0x14,0xee,0x4a,0x0e] # CHECK: vqrdmlah.s16 q0, q2, r10 @ encoding: [0x14,0xee,0x4a,0x0e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x14,0xee,0x4a,0x0e] [0x14,0xee,0x4a,0x0e]
# CHECK: vqrdmlah.s32 q0, q4, r11 @ encoding: [0x28,0xee,0x4b,0x0e] # CHECK: vqrdmlah.s32 q0, q4, r11 @ encoding: [0x28,0xee,0x4b,0x0e]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x28,0xee,0x4b,0x0e] [0x28,0xee,0x4b,0x0e]
# CHECK: vqrdmlah.u8 q0, q4, r2 @ encoding: [0x08,0xfe,0x42,0x0e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x08,0xfe,0x42,0x0e] [0x08,0xfe,0x42,0x0e]
# CHECK: vqrdmlah.u16 q0, q6, r1 @ encoding: [0x1c,0xfe,0x41,0x0e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x1c,0xfe,0x41,0x0e] [0x1c,0xfe,0x41,0x0e]
# CHECK: vqrdmlah.u32 q0, q4, r2 @ encoding: [0x28,0xfe,0x42,0x0e] # ERROR: [[@LINE+2]]:2: warning: invalid instruction encoding
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x28,0xfe,0x42,0x0e] [0x28,0xfe,0x42,0x0e]
# CHECK: viwdup.u8 q0, lr, r1, #1 @ encoding: [0x0f,0xee,0x60,0x0f] # CHECK: viwdup.u8 q0, lr, r1, #1 @ encoding: [0x0f,0xee,0x60,0x0f]
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
[0x0f,0xee,0x60,0x0f] [0x0f,0xee,0x60,0x0f]
# CHECK: viwdup.u16 q1, r10, r1, #8 @ encoding: [0x1b,0xee,0xe1,0x2f] # CHECK: viwdup.u16 q1, r10, r1, #8 @ encoding: [0x1b,0xee,0xe1,0x2f]
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