[mips] Implement sgt/sgtu pseudo instructions with immediate operand

[atanasyan]

Summary

The sgt/sgtu Dst, Src1, Src2/Imm pseudo instructions set register Dst to 1 if register Src1 is greater than Src2/Imm and to 0 otherwise.

[Petar.Avramovic]

LGTM.

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
                  const MCSubtargetInfo *STI);
 
   bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                  const MCSubtargetInfo *STI);
 
   bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                  const MCSubtargetInfo *STI);
 
+  bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+                    const MCSubtargetInfo *STI);
+
   bool expandRotation(MCInst &Inst, SMLoc IDLoc,
                       MCStreamer &Out, const MCSubtargetInfo *STI);
   bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                          const MCSubtargetInfo *STI);
   bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                        const MCSubtargetInfo *STI);
   bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                           const MCSubtargetInfo *STI);
MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   case Mips::Ush:
     return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   case Mips::Ulw:
   case Mips::Usw:
     return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   case Mips::NORImm:
   case Mips::NORImm64:
     return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+  case Mips::SGTImm:
+  case Mips::SGTUImm:
+  case Mips::SGTImm64:
+  case Mips::SGTUImm64:
+    return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   case Mips::SLTImm64:
     if (isInt<16>(Inst.getOperand(2).getImm())) {
       Inst.setOpcode(Mips::SLTi64);
       return MER_NotAMacro;
     }
     return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   case Mips::SLTUImm64:
     if (isInt<16>(Inst.getOperand(2).getImm())) {
bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI);
 
   if (DoMove)
     TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);
 
   return false;
 }
 
+bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+                                 const MCSubtargetInfo *STI) {
+  MipsTargetStreamer &TOut = getTargetStreamer();
+
+  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
+  assert(Inst.getOperand(0).isReg() &&
+         Inst.getOperand(1).isReg() &&
+         Inst.getOperand(2).isImm() && "Invalid instruction operand.");
+
+  unsigned DstReg = Inst.getOperand(0).getReg();
+  unsigned SrcReg = Inst.getOperand(1).getReg();
+  unsigned ImmReg = DstReg;
+  int64_t ImmValue = Inst.getOperand(2).getImm();
+  unsigned OpCode;
+
+  warnIfNoMacro(IDLoc);
+
+  switch (Inst.getOpcode()) {
+  case Mips::SGTImm:
+  case Mips::SGTImm64:
+    OpCode = Mips::SLT;
+    break;
+  case Mips::SGTUImm:
+  case Mips::SGTUImm64:
+    OpCode = Mips::SLTu;
+    break;
+  default:
+    llvm_unreachable("unexpected 'sgt' opcode with immediate");
+  }
+
+  if (DstReg == SrcReg) {
+    unsigned ATReg = getATReg(Inst.getLoc());
+    if (!ATReg)
+      return true;
+    ImmReg = ATReg;
+  }
+
+  if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
+                    false, IDLoc, Out, STI))
+    return true;
+
+  // $SrcReg > $ImmReg is equal to $ImmReg < $SrcReg
+  TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI);
+
+  return false;
+}
+
 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
                                          MCStreamer &Out,
                                          const MCSubtargetInfo *STI) {
   MipsTargetStreamer &TOut = getTargetStreamer();
 
   assert(Inst.getNumOperands() == 3 && "Invalid operand count");
   assert(Inst.getOperand(0).isReg() &&
          Inst.getOperand(1).isReg() &&

llvm/lib/Target/Mips/Mips64InstrInfo.td

 def : MipsInstAlias<"slt\t$rs, $imm", (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
                                                 imm64:$imm)>, GPR_64;
 def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs),
                                   (ins GPR64Opnd:$rt, imm64:$imm),
                                   "sltu\t$rs, $rt, $imm">, GPR_64;
 def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
                                                   imm64:$imm)>, GPR_64;
 
+def SGTImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
+                                 (ins GPR64Opnd:$rs, imm64:$imm),
+                                 "sgt\t$rd, $rs, $imm">, GPR_64;
+def : MipsInstAlias<"sgt $rs, $imm", (SGTImm64 GPR64Opnd:$rs,
+                                               GPR64Opnd:$rs,
+                                               imm64:$imm), 0>, GPR_64;
+
+def SGTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
+                                  (ins GPR64Opnd:$rs, imm64:$imm),
+                                  "sgtu\t$rd, $rs, $imm">, GPR_64;
+def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm64 GPR64Opnd:$rs,
+                                                 GPR64Opnd:$rs,
+                                                 imm64:$imm), 0>, GPR_64;
+
 def : MipsInstAlias<"rdhwr $rt, $rs",
                     (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64;

llvm/lib/Target/Mips/MipsInstrInfo.td

let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<"negu $rt",
                       (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>, ISA_MIPS1;
   def : MipsInstAlias<
           "sgt $rd, $rs, $rt",
           (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
   def : MipsInstAlias<
           "sgt $rs, $rt",
           (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
+
+  def SGTImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                 (ins GPR32Opnd:$rs, simm32:$imm),
+                                 "sgt\t$rd, $rs, $imm">, GPR_32;
+  def : MipsInstAlias<"sgt $rs, $imm", (SGTImm GPR32Opnd:$rs,
+                                               GPR32Opnd:$rs,
+                                               simm32:$imm), 0>,
+        GPR_32;
   def : MipsInstAlias<
           "sgtu $rd, $rs, $rt",
           (SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
   def : MipsInstAlias<
           "sgtu $$rs, $rt",
           (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
+
+  def SGTUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+                                  (ins GPR32Opnd:$rs, uimm32_coerced:$imm),
+                                  "sgtu\t$rd, $rs, $imm">, GPR_32;
+  def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm GPR32Opnd:$rs,
+                                                 GPR32Opnd:$rs,
+                                                 uimm32_coerced:$imm), 0>,
+        GPR_32;
+
   def : MipsInstAlias<
           "not $rt, $rs",
           (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MIPS1;
   def : MipsInstAlias<
           "not $rt",
           (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>, ISA_MIPS1;
 
   def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MIPS1;

llvm/test/MC/Mips/macro-sgt.s

+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
+
+sgt   $4, $5
+# CHECK: slt $4, $5, $4         # encoding: [0x00,0xa4,0x20,0x2a]
+sgt   $4, $5, $6
+# CHECK: slt $4, $6, $5         # encoding: [0x00,0xc5,0x20,0x2a]
+sgt   $4, $5, 16
+# CHECK: addiu $4, $zero, 16    # encoding: [0x24,0x04,0x00,0x10]
+# CHECK: slt   $4, $4, $5       # encoding: [0x00,0x85,0x20,0x2a]
+sgtu  $4, $5
+# CHECK: sltu $4, $5, $4        # encoding: [0x00,0xa4,0x20,0x2b]
+sgtu  $4, $5, $6
+# CHECK: sltu $4, $6, $5        # encoding: [0x00,0xc5,0x20,0x2b]
+sgtu  $4, $5, 16
+# CHECK: addiu $4, $zero, 16    # encoding: [0x24,0x04,0x00,0x10]
+# CHECK: sltu  $4, $4, $5       # encoding: [0x00,0x85,0x20,0x2b]
+
+sgt   $4, 16
+# CHECK: addiu $1, $zero, 16    # encoding: [0x24,0x01,0x00,0x10]
+# CHECK: slt   $4, $1, $4       # encoding: [0x00,0x24,0x20,0x2a]
+sgtu  $4, 16
+# CHECK: addiu $1, $zero, 16    # encoding: [0x24,0x01,0x00,0x10]
+# CHECK: sltu  $4, $1, $4       # encoding: [0x00,0x24,0x20,0x2b]

llvm/test/MC/Mips/macro-sgt64.s

+# RUN: not llvm-mc -arch=mips -mcpu=mips1 < %s 2>&1 \
+# RUN:   | FileCheck --check-prefix=MIPS32 %s
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
+# RUN:   | FileCheck --check-prefix=MIPS64 %s
+
+sgt   $4, $5, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori  $4, $zero, 32768  # encoding: [0x34,0x04,0x80,0x00]
+# MIPS64: dsll $4, $4, 17        # encoding: [0x00,0x04,0x24,0x78]
+# MIPS64: slt  $4, $4, $5        # encoding: [0x00,0x85,0x20,0x2a]
+sgtu  $4, $5, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori  $4, $zero, 32768  # encoding: [0x34,0x04,0x80,0x00]
+# MIPS64: dsll $4, $4, 17        # encoding: [0x00,0x04,0x24,0x78]
+# MIPS64: sltu $4, $4, $5        # encoding: [0x00,0x85,0x20,0x2b]
+sgt   $4, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori  $1, $zero, 32768  # encoding: [0x34,0x01,0x80,0x00]
+# MIPS64: dsll $1, $1, 17        # encoding: [0x00,0x01,0x0c,0x78]
+# MIPS64: slt  $4, $1, $4        # encoding: [0x00,0x24,0x20,0x2a]
+sgtu  $4, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori  $1, $zero, 32768  # encoding: [0x34,0x01,0x80,0x00]
+# MIPS64: dsll $1, $1, 17        # encoding: [0x00,0x01,0x0c,0x78]
+# MIPS64: sltu $4, $1, $4        # encoding: [0x00,0x24,0x20,0x2b]