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[AArch64] Fix scalar vuqadd intrinsics operands
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Authored by dnsampaio on Jul 5 2019, 4:23 AM.

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Summary

Change the vuqadd scalar instrinsics to have the second argument as unsigned values, not signed,
accordingly to https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics

So now the compiler correctly warns that a undefined negative float conversion is being done.

Diff Detail

Repository
rL LLVM

Event Timeline

dnsampaio created this revision.Jul 5 2019, 4:23 AM
dnsampaio updated this revision to Diff 208144.Jul 5 2019, 4:29 AM
  • Fix previously existing tests
john.brawn accepted this revision.Jul 5 2019, 7:02 AM
john.brawn added a subscriber: john.brawn.

LGTM, with one nitpick.

test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c
2 ↗(On Diff #208144)

I don't think the -fallow-half-arguments-and-returns here is necessary.

This revision is now accepted and ready to land.Jul 5 2019, 7:02 AM
This revision was automatically updated to reflect the committed changes.
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