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[AArch64] Fix vsqadd scalar intrinsics operands
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Authored by dnsampaio on Jul 5 2019, 3:59 AM.

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Summary

Change the vsqadd scalar instrinsics to have the second argument as signed values, not unsigned,
accordingly to https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics

The existing unsigned argument can cause faulty code as negative float to unsigned conversion is
undefined, which llvm/clang optimizes away.

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rL LLVM

Event Timeline

dnsampaio created this revision.Jul 5 2019, 3:59 AM
john.brawn accepted this revision.Jul 5 2019, 6:31 AM
john.brawn added a subscriber: john.brawn.

LGTM, with a couple of nitpicks.

The existing unsigned argument can cause faulty code as float to unsigned conversion is undefined,
which llvm/clang optimizes away.

It's specifically negative float to unsigned that's undefined.

test/CodeGen/aarch64-neon-vsqadd-float-conversion.c
2 ↗(On Diff #208137)

I don't think -fallow-half-arguments-and-returns is necessary.

This revision is now accepted and ready to land.Jul 5 2019, 6:31 AM
dnsampaio edited the summary of this revision. (Show Details)Jul 8 2019, 1:19 AM
This revision was automatically updated to reflect the committed changes.
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