[PowerPC] Replace float load/store pair with integer load/store pair when it's only used in load/store

[• wuzish]

Summary

Replace float load/store pair with integer load/store pair when it's only used in load/store, because float load/store instructions cost more cycles then integer load/store.

A typical scenario is when there is a call with more than 13 float arguments passing, we need pass them by stack. So we need a load/store pair to do such memory operation if the variable is global variable.

[• wuzish]

gentle pin... It's a follow-up of https://reviews.llvm.org/D60601

[jsji]

In theory this should be a good idea, especially with P9, we can remove the "restrict" dispatch constraints for lfs/lfd.

Can you get some performance data w and w/o this?

Request change to split the NFC patch out. Thanks.

lib/Target/PowerPC/PPCISelLowering.h

832 ↗

(On Diff #207979)

Please add some comments here about why we deem it is profitable?

833 ↗

(On Diff #207979)

Maybe it would be better to be explicit here, check for f32 and f64 only?

test/CodeGen/PowerPC/float-load-store-pair.ll

4 ↗

(On Diff #207979)

Please commit the testcase in a NFC patch first, then only show difference here.

[• wuzish]

Address comments

[• wuzish]

This comment was removed by • wuzish.

[• wuzish]

After run bmk 2017 cpu for fortran and c/c++, there is some noise, no obvious degression. Some have little improvement about 1%~2%.

[• wuzish]

Gentle pin..

[jsji]

LGTM.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h

public:
     /// to just the constant itself.
     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                            Type *Ty) const override;
 
     bool convertSelectOfConstantsToMath(EVT VT) const override {
       return true;
     }
 
+    bool isDesirableToTransformToIntegerOp(unsigned Opc,
+                                           EVT VT) const override {
+      // Only handle float load/store pair because float(fpr) load/store
+      // instruction has more cycles than integer(gpr) load/store in PPC.
+      if (Opc != ISD::LOAD && Opc != ISD::STORE)
+        return false;
+      if (VT != MVT::f32 && VT != MVT::f64)
+        return false;
+
+      return true; 
+    }
+
     // Returns true if the address of the global is stored in TOC entry.
     bool isAccessedAsGotIndirect(SDValue N) const;
 
     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
                             const CallInst &I,
                             MachineFunction &MF,

llvm/trunk/test/CodeGen/PowerPC/float-load-store-pair.ll

 ; CHECK-NEXT:    lfd 7, a7@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a8@toc@ha
 ; CHECK-NEXT:    lfd 8, a8@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a9@toc@ha
 ; CHECK-NEXT:    lfd 9, a9@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a10@toc@ha
 ; CHECK-NEXT:    lfd 10, a10@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a11@toc@ha
+; CHECK-NEXT:    addis 6, 2, a17@toc@ha
+; CHECK-NEXT:    addis 5, 2, a16@toc@ha
+; CHECK-NEXT:    addi 6, 6, a17@toc@l
+; CHECK-NEXT:    addi 5, 5, a16@toc@l
+; CHECK-NEXT:    lxvx 34, 0, 6
+; CHECK-NEXT:    addis 4, 2, a15@toc@ha
+; CHECK-NEXT:    lxvx 0, 0, 5
+; CHECK-NEXT:    ld 4, a15@toc@l(4)
+; CHECK-NEXT:    li 5, 168
 ; CHECK-NEXT:    lfd 11, a11@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a12@toc@ha
 ; CHECK-NEXT:    lfd 12, a12@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a13@toc@ha
 ; CHECK-NEXT:    lfd 13, a13@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a14@toc@ha
-; CHECK-NEXT:    lfd 0, a14@toc@l(3)
-; CHECK-NEXT:    addis 3, 2, a15@toc@ha
-; CHECK-NEXT:    addis 4, 2, a17@toc@ha
-; CHECK-NEXT:    addi 4, 4, a17@toc@l
-; CHECK-NEXT:    lxsd 2, a15@toc@l(3)
-; CHECK-NEXT:    addis 3, 2, a16@toc@ha
-; CHECK-NEXT:    addi 3, 3, a16@toc@l
-; CHECK-NEXT:    lxvx 36, 0, 4
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    li 3, 168
-; CHECK-NEXT:    stxvx 36, 1, 3
-; CHECK-NEXT:    li 3, 152
-; CHECK-NEXT:    stxvx 35, 1, 3
-; CHECK-NEXT:    stxsd 2, 144(1)
-; CHECK-NEXT:    stfd 0, 136(1)
+; CHECK-NEXT:    ld 3, a14@toc@l(3)
+; CHECK-NEXT:    stxvx 34, 1, 5
+; CHECK-NEXT:    li 5, 152
+; CHECK-NEXT:    stxvx 0, 1, 5
+; CHECK-NEXT:    std 4, 144(1)
+; CHECK-NEXT:    std 3, 136(1)
 ; CHECK-NEXT:    bl _Z3fooddddddddddddddd
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    addi 1, 1, 192
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 %1 = load double, double* @a1, align 8

llvm/trunk/test/CodeGen/PowerPC/ppc64-smallarg.ll

 
 define void @caller2() {
 entry:
   %0 = load float, float* @gf, align 4
   %call = tail call float @test2(float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float %0)
   ret void
 }
 ; CHECK: @caller2
-; CHECK: stfs {{[0-9]+}}, 156(1)
+; CHECK: std {{[0-9]+}}, 16(1)
 ; CHECK: bl test2
 
 declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float)
 

llvm/trunk/test/CodeGen/PowerPC/ppc64le-smallarg.ll

 
 define void @caller2() {
 entry:
   %0 = load float, float* @gf, align 4
   %call = tail call float @test2(float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float %0)
   ret void
 }
 ; CHECK: @caller2
-; CHECK: stfs {{[0-9]+}}, 136({{[0-9]+}})
+; CHECK: std {{[0-9]+}}, 16({{[0-9]+}})
 ; CHECK: bl test2
 
 declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float)
 

llvm/trunk/test/CodeGen/PowerPC/pwr7-gt-nop.ll

entry:
   %0 = load float, float* %b, align 4
   store float %0, float* %a, align 4
   %1 = load float, float* %c, align 4
   store float %1, float* %b, align 4
   %2 = load float, float* %a, align 4
   store float %2, float* %d, align 4
   ret void
 
-; CHECK: lfs [[REG1:[0-9]+]], 0(4)
-; CHECK: stfs [[REG1]], 0(3)
-; CHECK: lfs [[REG2:[0-9]+]], 0(5)
-; CHECK: stfs [[REG2]], 0(4)
-; CHECK: lfs [[REG3:[0-9]+]], 0(3)
-; CHECK: stfs [[REG3]], 0(6)
+; CHECK: lwz [[REG1:[0-9]+]], 0(4)
+; CHECK: stw [[REG1]], 0(3)
+; CHECK: lwz [[REG2:[0-9]+]], 0(5)
+; CHECK: stw [[REG2]], 0(4)
+; CHECK: lwz [[REG3:[0-9]+]], 0(3)
+; CHECK: stw [[REG3]], 0(6)
 ; CHECK: blr
 }
 
 attributes #0 = { nounwind }