[mips][microMIPS] Implement LWSP and SWSP instructions

[jkolek]

Summary

Implement microMIPS 16-bit LWSP and SWSP instructions.

[jkolek]

Reused existing assembler operand predicate method isMemWithUimmOffsetSP.

[sstankovic]

test/MC/Mips/micromips-16-bit-instructions.s

70

This is another case where there is a difference between microMIPS reference documentation and gas. gas doesn't support lwsp and swsp mnemonics. gas emits these two encodings (0x4868 and 0xc89f ) when assembling following two instructions

lw $3, 32($sp)
sw $4, 124($sp)

I suggest that you (at least for now) print these instructions using the mnemonics that gas supports, and add a comment in the patch that this problem exists.

[jkolek]

Implemented assembler pseudo instructions LW/SW: If offset fits into 7 bits and base register is SP then create LWSP/SWSP encoding instead of LW/SW.

[sstankovic]

This patch doesn't correctly handle the case when (offset % 4) != 0. For example, for the following instruction

lw v1,123(sp)

instead of emitting 32-bit "lw v1,123(sp)" the patch emits 16-bit "lw v1,120(sp)"

Please include this instruction in the tests.

[sstankovic]

LGTM

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
                                     uint64_t Address, const void *Decoder);
 
 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
                                     unsigned Insn,
                                     uint64_t Address,
                                     const void *Decoder);
 
+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
+                                          unsigned Insn,
+                                          uint64_t Address,
+                                          const void *Decoder);
+
 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
                                      const void *Decoder);
 
 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
switch (Inst.getOpcode()) {
     case Mips::SW16_MM:
       Inst.addOperand(MCOperand::CreateImm(Offset << 2));
       break;
   }
 
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
+                                          unsigned Insn,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  unsigned Offset = Insn & 0x1F;
+  unsigned Reg = fieldFromInstruction(Insn, 5, 5);
+
+  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
+
+  Inst.addOperand(MCOperand::CreateReg(Reg));
+  Inst.addOperand(MCOperand::CreateReg(Mips::SP));
+  Inst.addOperand(MCOperand::CreateImm(Offset << 2));
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
                                      const void *Decoder) {
   int Offset = SignExtend32<12>(Insn & 0x0fff);
   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
                                 SmallVectorImpl<MCFixup> &Fixups,
                                 const MCSubtargetInfo &STI) const;
   unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
                                     SmallVectorImpl<MCFixup> &Fixups,
                                     const MCSubtargetInfo &STI) const;
   unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
                                     SmallVectorImpl<MCFixup> &Fixups,
                                     const MCSubtargetInfo &STI) const;
+  unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
+                                      SmallVectorImpl<MCFixup> &Fixups,
+                                      const MCSubtargetInfo &STI) const;
   unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
   unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
                                   SmallVectorImpl<MCFixup> &Fixups,
                                   const MCSubtargetInfo &STI) const;
   unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
                               SmallVectorImpl<MCFixup> &Fixups,

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
                                        Fixups, STI) << 4;
   unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
                                        Fixups, STI) >> 2;
 
   return (OffBits & 0xF) | RegBits;
 }
 
 unsigned MipsMCCodeEmitter::
+getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
+                           SmallVectorImpl<MCFixup> &Fixups,
+                           const MCSubtargetInfo &STI) const {
+  // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
+  assert(MI.getOperand(OpNo).isReg() &&
+         MI.getOperand(OpNo).getReg() == Mips::SP &&
+         "Unexpected base register!");
+  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
+                                       Fixups, STI) >> 2;
+
+  return OffBits & 0x1F;
+}
+
+unsigned MipsMCCodeEmitter::
 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
                       SmallVectorImpl<MCFixup> &Fixups,
                       const MCSubtargetInfo &STI) const {
   // opNum can be invalid if instruction had reglist as operand.
   // MemOperand is always last operand of instruction (base + offset).
   switch (MI.getOpcode()) {
   default:
     break;

lib/Target/Mips/MicroMipsInstrFormats.td

class LOAD_STORE_FM_MM16<bits<6> op> {
   bits<16> Inst;
 
   let Inst{15-10} = op;
   let Inst{9-7}   = rt;
   let Inst{6-4}   = addr{6-4};
   let Inst{3-0}   = addr{3-0};
 }
 
+class LOAD_STORE_SP_FM_MM16<bits<6> op> {
+  bits<5> rt;
+  bits<5> offset;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = op;
+  let Inst{9-5}   = rt;
+  let Inst{4-0}   = offset;
+}
+
 class ADDIUS5_FM_MM16 {
   bits<5> rd;
   bits<4> imm;
 
   bits<16> Inst;
 
   let Inst{15-10} = 0x13;
   let Inst{9-5}   = rd;

lib/Target/Mips/MicroMipsInstrInfo.td

 def mem_mm_4_lsl1 : mem_mm_4_generic {
   let EncoderMethod = "getMemEncodingMMImm4Lsl1";
 }
 
 def mem_mm_4_lsl2 : mem_mm_4_generic {
   let EncoderMethod = "getMemEncodingMMImm4Lsl2";
 }
 
+def MicroMipsMemSPAsmOperand : AsmOperandClass {
+  let Name = "MicroMipsMemSP";
+  let RenderMethod = "addMemOperands";
+  let ParserMethod = "parseMemOperand";
+  let PredicateMethod = "isMemWithUimmOffsetSP<7>";
+}
+
+def mem_mm_sp_imm5_lsl2 : Operand<i32> {
+  let PrintMethod = "printMemOperand";
+  let MIOperandInfo = (ops GPR32:$base, simm5:$offset);
+  let OperandType = "OPERAND_MEMORY";
+  let ParserMatchClass = MicroMipsMemSPAsmOperand;
+  let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
+}
+
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops GPR32, simm12);
   let EncoderMethod = "getMemEncodingMMImm12";
   let ParserMatchClass = MipsMemAsmOperand;
   let OperandType = "OPERAND_MEMORY";
 }
 
class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
                 SDPatternOperator OpNode, InstrItinClass Itin,
                 Operand MemOpnd> :
   MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
                   !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
   let DecoderMethod = "DecodeMemMMImm4";
   let mayStore = 1;
 }
 
+class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
+                 Operand MemOpnd> :
+  MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
+                  !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
+  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
+  let canFoldAsLoad = 1;
+  let mayLoad = 1;
+}
+
+class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
+                  Operand MemOpnd> :
+  MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
+                  !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
+  let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
+  let mayStore = 1;
+}
+
 class AddImmUR2<string opstr, RegisterOperand RO> :
   MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
                   !strconcat(opstr, "\t$rd, $rs, $imm"),
                   [], NoItinerary, FrmR> {
   let isCommutable = 1;
 }
 
 class AddImmUS5<string opstr, RegisterOperand RO> :
def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
                       LOAD_STORE_FM_MM16<0x1a>;
 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
                         II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
                         II_SH, mem_mm_4_lsl1>,
                         LOAD_STORE_FM_MM16<0x2a>;
 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
                         mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
+def LWSP_MM : LoadSPMM16<"lwsp", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
+              LOAD_STORE_SP_FM_MM16<0x12>;
+def SWSP_MM : StoreSPMM16<"swsp", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
+              LOAD_STORE_SP_FM_MM16<0x32>;
 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
 def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd, immLi16>,

test/MC/Disassembler/Mips/micromips.txt

 # CHECK: addiur2 $6, $7, -1
 0x6f 0x7e
 
 # CHECK: addiur2 $6, $7, 12
 0x6f 0x76
 
 # CHECK: addius5 $7, -2
 0x4c 0xfc
+
+# CHECK: lwsp $3, 32($sp)
+0x48 0x68
+
+# CHECK: swsp $4, 124($sp)
+0xc8 0x9f

test/MC/Disassembler/Mips/micromips_le.txt

 # CHECK: addiur2 $6, $7, -1
 0x7e 0x6f
 
 # CHECK: addiur2 $6, $7, 12
 0x76 0x6f
 
 # CHECK: addius5 $7, -2
 0xfc 0x4c
+
+# CHECK: lwsp $3, 32($sp)
+0x68 0x48
+
+# CHECK: swsp $4, 124($sp)
+0x9f 0xc8

test/MC/Mips/micromips-16-bit-instructions.s

 # CHECK-EL: lbu16   $3, 4($17)      # encoding: [0x94,0x09]
 # CHECK-EL: lbu16   $3, -1($16)     # encoding: [0x8f,0x09]
 # CHECK-EL: lhu16   $3, 4($16)      # encoding: [0x82,0x29]
 # CHECK-EL: lw16    $4, 8($17)      # encoding: [0x12,0x6a]
 # CHECK-EL: sb16    $3, 4($16)      # encoding: [0x84,0x89]
 # CHECK-EL: sh16    $4, 8($17)      # encoding: [0x14,0xaa]
 # CHECK-EL: sw16    $4, 4($17)      # encoding: [0x11,0xea]
 # CHECK-EL: sw16    $zero, 4($17)   # encoding: [0x11,0xe8]
+# CHECK-EL: lwsp    $3, 32($sp)     # encoding: [0x68,0x48]
+# CHECK-EL: swsp    $4, 124($sp)    # encoding: [0x9f,0xc8]
 # CHECK-EL: li16    $3, -1          # encoding: [0xff,0xed]
 # CHECK-EL: li16    $3, 126         # encoding: [0xfe,0xed]
 # CHECK-EL: addiur1sp $7, 4         # encoding: [0x83,0x6f]
 # CHECK-EL: addiur2 $6, $7, -1      # encoding: [0x7e,0x6f]
 # CHECK-EL: addiur2 $6, $7, 12      # encoding: [0x76,0x6f]
 # CHECK-EL: addius5 $7, -2          # encoding: [0xfc,0x4c]
 # CHECK-EL: addiusp -16             # encoding: [0xf9,0x4f]
 # CHECK-EL: mfhi    $9              # encoding: [0x09,0x46]

 # CHECK-EB: lbu16   $3, 4($17)      # encoding: [0x09,0x94]
 # CHECK-EB: lbu16   $3, -1($16)     # encoding: [0x09,0x8f]
 # CHECK-EB: lhu16   $3, 4($16)      # encoding: [0x29,0x82]
 # CHECK-EB: lw16    $4, 8($17)      # encoding: [0x6a,0x12]
 # CHECK-EB: sb16    $3, 4($16)      # encoding: [0x89,0x84]
 # CHECK-EB: sh16    $4, 8($17)      # encoding: [0xaa,0x14]
 # CHECK-EB: sw16    $4, 4($17)      # encoding: [0xea,0x11]
 # CHECK-EB: sw16    $zero, 4($17)   # encoding: [0xe8,0x11]
+# CHECK-EB: lwsp    $3, 32($sp)     # encoding: [0x48,0x68]
+# CHECK-EB: swsp    $4, 124($sp)    # encoding: [0xc8,0x9f]
 # CHECK-EB: li16    $3, -1          # encoding: [0xed,0xff]
 # CHECK-EB: li16    $3, 126         # encoding: [0xed,0xfe]
 # CHECK-EB: addiur1sp $7, 4         # encoding: [0x6f,0x83]
 # CHECK-EB: addiur2 $6, $7, -1      # encoding: [0x6f,0x7e]
 # CHECK-EB: addiur2 $6, $7, 12      # encoding: [0x6f,0x76]
 # CHECK-EB: addius5 $7, -2          # encoding: [0x4c,0xfc]
 # CHECK-EB: addiusp -16             # encoding: [0x4f,0xf9]
 # CHECK-EB: mfhi    $9              # encoding: [0x46,0x09]
# CHECK-EB: sdbbp16 14              # encoding: [0x46,0xce]
     lbu16   $3, 4($17)
     lbu16   $3, -1($16)
     lhu16   $3, 4($16)
     lw16    $4, 8($17)
     sb16    $3, 4($16)
     sh16    $4, 8($17)
     sw16    $4, 4($17)
     sw16    $0, 4($17)
+    lwsp    $3, 32($sp)
+    swsp    $4, 124($sp)
     li16    $3, -1
     li16    $3, 126
     addiur1sp $7, 4
     addiur2 $6, $7, -1
     addiur2 $6, $7, 12
     addius5 $7, -2
     addiusp -16
     mfhi    $9

test/MC/Mips/micromips-invalid.s

# RUN: FileCheck %s < %t1
   sh16  $16, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sw16  $16, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   lbu16 $16, 8($9)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   lhu16 $16, 4($9)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   lw16  $17, 8($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sb16  $7, 4($9)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sh16  $7, 8($9)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   sw16  $7, 4($10)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  lwsp  $3, -2($sp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  swsp  $4, 128($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  lwsp  $3, 32($28)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  swsp  $3, 32($28)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction