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Differential D63997

AMDGPU/GlobalISel: Custom lower control flow intrinsics
ClosedPublic

Authored by arsenm on Jul 1 2019, 5:44 AM.

Details

Reviewers
tstellar
nhaehnle
Summary

Replace the brcond for the 2 cases that act as branches. For now
follow how the current system works, although I think we can
eventually get rid of the pseudos.

Diff Detail

Event Timeline

arsenm created this revision.Jul 1 2019, 5:44 AM
Herald added subscribers: Petar.Avramovic, t-tye, tpr and 7 others. · View Herald TranscriptJul 1 2019, 5:44 AM
arsenm added a parent revision: D31359: [GlobalISel]: Allow backends to custom legalize Intrinsics.Jul 1 2019, 5:44 AM
tstellar accepted this revision.Jul 1 2019, 7:44 AM

LGTM.

This revision is now accepted and ready to land.Jul 1 2019, 7:44 AM
arsenm closed this revision.Jul 1 2019, 11:40 AM

r364832

Revision Contents

PathSize
lib/
Target/
AMDGPU/
5 lines
94 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
73 lines
103 lines

Diff 207273

lib/Target/AMDGPU/AMDGPULegalizerInfo.h

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const;
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder, bool Signed) const; MachineIRBuilder &MIRBuilder, bool Signed) const;
bool legalizeBRCOND(MachineInstr &MI, MachineRegisterInfo &MRI, bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder) const; MachineIRBuilder &MIRBuilder) const override;
}; };
} // End llvm namespace. } // End llvm namespace.
#endif #endif

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
const std::initializer_list<LLT> AddrSpaces64 = { const std::initializer_list<LLT> AddrSpaces64 = {
GlobalPtr, ConstantPtr, FlatPtr GlobalPtr, ConstantPtr, FlatPtr
}; };
const std::initializer_list<LLT> AddrSpaces32 = { const std::initializer_list<LLT> AddrSpaces32 = {
LocalPtr, PrivatePtr LocalPtr, PrivatePtr
}; };
setAction({G_BRCOND, S1}, Custom); setAction({G_BRCOND, S1}, Legal);
// TODO: All multiples of 32, vectors of pointers, all v2s16 pairs, more // TODO: All multiples of 32, vectors of pointers, all v2s16 pairs, more
// elements for v3s16 // elements for v3s16
getActionDefinitionsBuilder(G_PHI) getActionDefinitionsBuilder(G_PHI)
.legalFor({S32, S64, V2S16, V4S16, S1, S128, S256}) .legalFor({S32, S64, V2S16, V4S16, S1, S128, S256})
.legalFor(AllS32Vectors) .legalFor(AllS32Vectors)
.legalFor(AllS64Vectors) .legalFor(AllS64Vectors)
.legalFor(AddrSpaces64) .legalFor(AddrSpaces64)
▲ Show 20 Lines • Show All 568 Lines • ▼ Show 20 Linesbool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI,
case TargetOpcode::G_FCEIL: case TargetOpcode::G_FCEIL:
return legalizeFceil(MI, MRI, MIRBuilder); return legalizeFceil(MI, MRI, MIRBuilder);
case TargetOpcode::G_INTRINSIC_TRUNC: case TargetOpcode::G_INTRINSIC_TRUNC:
return legalizeIntrinsicTrunc(MI, MRI, MIRBuilder); return legalizeIntrinsicTrunc(MI, MRI, MIRBuilder);
case TargetOpcode::G_SITOFP: case TargetOpcode::G_SITOFP:
return legalizeITOFP(MI, MRI, MIRBuilder, true); return legalizeITOFP(MI, MRI, MIRBuilder, true);
case TargetOpcode::G_UITOFP: case TargetOpcode::G_UITOFP:
return legalizeITOFP(MI, MRI, MIRBuilder, false); return legalizeITOFP(MI, MRI, MIRBuilder, false);
case TargetOpcode::G_BRCOND:
return legalizeBRCOND(MI, MRI, MIRBuilder);
default: default:
return false; return false;
} }
llvm_unreachable("expected switch to return"); llvm_unreachable("expected switch to return");
} }
Register AMDGPULegalizerInfo::getSegmentAperture( Register AMDGPULegalizerInfo::getSegmentAperture(
▲ Show 20 Lines • Show All 291 Lines • ▼ Show 20 Lines auto LdExp = B.buildIntrinsic(Intrinsic::amdgcn_ldexp, {S64}, false)
.addUse(ThirtyTwo.getReg(0)); .addUse(ThirtyTwo.getReg(0));
// TODO: Should this propagate fast-math-flags? // TODO: Should this propagate fast-math-flags?
B.buildFAdd(Dst, LdExp, CvtLo); B.buildFAdd(Dst, LdExp, CvtLo);
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
bool AMDGPULegalizerInfo::legalizeBRCOND(MachineInstr &MI, // Return the use branch instruction, otherwise null if the usage is invalid.
static MachineInstr *verifyCFIntrinsic(MachineInstr &MI,
MachineRegisterInfo &MRI) {
Register CondDef = MI.getOperand(0).getReg();
if (!MRI.hasOneNonDBGUse(CondDef))
return nullptr;
MachineInstr &UseMI = *MRI.use_instr_nodbg_begin(CondDef);
return UseMI.getParent() == MI.getParent() &&
UseMI.getOpcode() == AMDGPU::G_BRCOND ? &UseMI : nullptr;
}
bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
MachineRegisterInfo &MRI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const { MachineIRBuilder &B) const {
// TODO: Maybe it would be better to represent this as an exec reg bank only // Replace the use G_BRCOND with the exec manipulate and branch pseudos.
// produced by the control flow mask intrinsics apply this during switch (MI.getOperand(MI.getNumExplicitDefs()).getIntrinsicID()) {
// regbankselect, instead of hoping we can always find the intrinsic defining case Intrinsic::amdgcn_if: {
// the condition. TODO: Could we lower this on the intrinsic, and replace the if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI)) {
// branch opcode and see if the use/def mismatch? const SIRegisterInfo *TRI
Register CondReg = MI.getOperand(0).getReg(); = static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
MachineBasicBlock *DestBB = MI.getOperand(1).getMBB();
B.setInstr(*BrCond);
// FIXME: Should we be trying to figure out if the condition was negated like Register Def = MI.getOperand(1).getReg();
// in SelectionDAG? Register Use = MI.getOperand(3).getReg();
MachineInstr *CondDef = getOpcodeDef(AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS, B.buildInstr(AMDGPU::SI_IF)
CondReg, MRI); .addDef(Def)
if (!CondDef) .addUse(Use)
.addMBB(BrCond->getOperand(1).getMBB());
MRI.setRegClass(Def, TRI->getWaveMaskRegClass());
MRI.setRegClass(Use, TRI->getWaveMaskRegClass());
MI.eraseFromParent();
BrCond->eraseFromParent();
return true; return true;
}
B.setInstr(MI); return false;
}
case Intrinsic::amdgcn_loop: {
if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI)) {
const SIRegisterInfo *TRI
= static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
// FIXME: Probably can just directly emit some of the correct exec B.setInstr(*BrCond);
// modifications here and get rid of SILowerControlFlow. Register Reg = MI.getOperand(2).getReg();
switch (CondDef->getOperand(CondDef->getNumExplicitDefs()).getIntrinsicID()) {
case Intrinsic::amdgcn_if:
B.buildInstr(AMDGPU::SI_IF)
.addDef(CondDef->getOperand(1).getReg())
.addUse(CondDef->getOperand(3).getReg())
.addMBB(DestBB);
CondDef->eraseFromParent();
break;
case Intrinsic::amdgcn_loop:
B.buildInstr(AMDGPU::SI_LOOP) B.buildInstr(AMDGPU::SI_LOOP)
.addUse(CondDef->getOperand(2).getReg()) .addUse(Reg)
.addMBB(DestBB); .addMBB(BrCond->getOperand(1).getMBB());
CondDef->eraseFromParent(); MI.eraseFromParent();
break; BrCond->eraseFromParent();
MRI.setRegClass(Reg, TRI->getWaveMaskRegClass());
return true;
}
return false;
}
default: default:
return true; return true;
} }
MI.eraseFromParent();
return true; return true;
} }

test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir

  • This file was added.
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s
# Make sure incorrect usage of control flow intrinsics fails to select in case some transform separated the intrinsic from its branch.
# ERR: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_different_block)
# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_brcond_user)
# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_multi_user)
# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_condition)
---
name: brcond_si_if_different_block
body: |
bb.0:
successors: %bb.1
liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
bb.1:
G_BRCOND %3, %bb.1
...
---
name: si_if_not_brcond_user
body: |
bb.0:
liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
%5:_(s32) = G_SELECT %3, %0, %1
S_ENDPGM 0, implicit %5
...
---
name: si_if_multi_user
body: |
bb.0:
liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
%5:_(s32) = G_SELECT %3, %0, %1
G_BRCOND %3, %bb.1
bb.1:
S_ENDPGM 0, implicit %5
...
---
name: si_if_not_condition
body: |
bb.0:
liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
%5:_(s1) = G_CONSTANT i1 true
%6:_(s1) = G_XOR %3, %5
G_BRCOND %6, %bb.1
bb.1:
...

test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE32 %s
--- ---
name: legal_brcond name: legal_brcond_vcc
body: | body: |
; CHECK-LABEL: name: legal_brcond ; WAVE64-LABEL: name: legal_brcond_vcc
; CHECK: bb.0.entry: ; WAVE64: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; WAVE64: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] ; WAVE64: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1 ; WAVE64: G_BRCOND [[ICMP]](s1), %bb.1
; CHECK: bb.1: ; WAVE64: bb.1:
bb.0.entry: ; WAVE32-LABEL: name: legal_brcond_vcc
; WAVE32: bb.0:
; WAVE32: successors: %bb.1(0x80000000)
; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32: G_BRCOND [[ICMP]](s1), %bb.1
; WAVE32: bb.1:
bb.0:
successors: %bb.1 successors: %bb.1
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1 %2:_(s1) = G_ICMP intpred(ne), %0, %1
G_BRCOND %2, %bb.1 G_BRCOND %2, %bb.1
bb.1: bb.1:
... ...
--- ---
name: legal_brcond_scc name: legal_brcond_scc
body: | body: |
; CHECK-LABEL: name: legal_brcond_scc ; WAVE64-LABEL: name: legal_brcond_scc
; CHECK: bb.0: ; WAVE64: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; WAVE64: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] ; WAVE64: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1 ; WAVE64: G_BRCOND [[ICMP]](s1), %bb.1
; CHECK: bb.1: ; WAVE64: bb.1:
; WAVE32-LABEL: name: legal_brcond_scc
; WAVE32: bb.0:
; WAVE32: successors: %bb.1(0x80000000)
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; WAVE32: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
; WAVE32: G_BRCOND [[ICMP]](s1), %bb.1
; WAVE32: bb.1:
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:scc(s1) = G_ICMP intpred(eq), %0, %1 %2:scc(s1) = G_ICMP intpred(eq), %0, %1
G_BRCOND %2, %bb.1 G_BRCOND %2, %bb.1
bb.1: bb.1:
... ...
--- ---
name: brcond_si_if name: brcond_si_if
body: | body: |
; CHECK-LABEL: name: brcond_si_if ; WAVE64-LABEL: name: brcond_si_if
; CHECK: bb.0: ; WAVE64: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; WAVE64: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] ; WAVE64: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[SI_IF:%[0-9]+]]:_(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec ; WAVE64: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; CHECK: bb.1: ; WAVE64: bb.1:
; WAVE32-LABEL: name: brcond_si_if
; WAVE32: bb.0:
; WAVE32: successors: %bb.1(0x80000000)
; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; WAVE32: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32: bb.1:
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s1) = G_ICMP intpred(ne), %0, %1 %2:_(s1) = G_ICMP intpred(ne), %0, %1
%3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
G_BRCOND %3, %bb.1 G_BRCOND %3, %bb.1
bb.1: bb.1:
... ...
--- ---
name: brcond_si_loop name: brcond_si_loop
body: | body: |
; CHECK-LABEL: name: brcond_si_loop ; WAVE64-LABEL: name: brcond_si_loop
; CHECK: bb.0: ; WAVE64: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; WAVE64: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; WAVE64: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; WAVE64: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1 ; WAVE64: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
; CHECK: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec ; WAVE64: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; CHECK: bb.1: ; WAVE64: bb.1:
; WAVE32-LABEL: name: brcond_si_loop
; WAVE32: bb.0:
; WAVE32: successors: %bb.1(0x80000000)
; WAVE32: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; WAVE32: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
; WAVE32: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
; WAVE32: bb.1:
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s64) = COPY $sgpr0_sgpr1 %2:_(s64) = COPY $sgpr0_sgpr1
%3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
G_BRCOND %3, %bb.1 G_BRCOND %3, %bb.1
bb.1: bb.1:
... ...