[PowerPC] Implement the areMemAccessesTriviallyDisjoint hook

[steven.zhang]

Summary

This hook it is trying to tell, even without aliasing information, that two MIs access different memory addresses. This function returns true if two MIs access different memory addresses and false otherwise.

After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition.

There is no perf impact for spec2017 with this patch.

[jsji]

LGTM except for some minor comments update, you can update them before commit.
Thanks for implementing this hook, it should improve scheduling in general.

llvm/lib/Target/PowerPC/PPCInstrInfo.h

361 ↗

(On Diff #206577)

This is a little confusing to me, it is easy to read it as retrieve ... from ....
Maybe something like get the base operand, byte offset of an instruction and the memory width?

There are 2-3 similar ones in PPCInstrInfo.cpp as well.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrInfo.h

361 ↗

(On Diff #206577)

ok, I will update it.

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h

public:
 
   bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
                       unsigned &SrcReg2, int &Mask, int &Value) const override;
 
   bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
                             unsigned SrcReg2, int Mask, int Value,
                             const MachineRegisterInfo *MRI) const override;
 
+
+  /// Return true if get the base operand, byte offset of an instruction and
+  /// the memory width. Width is the size of memory that is being
+  /// loaded/stored (e.g. 1, 2, 4, 8).
+  bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
+                                    const MachineOperand *&BaseOp,
+                                    int64_t &Offset, unsigned &Width,
+                                    const TargetRegisterInfo *TRI) const;
+
+  /// Return true if two MIs access different memory addresses and false
+  /// otherwise
+  bool
+  areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
+                                  const MachineInstr &MIb,
+                                  AliasAnalysis *AA = nullptr) const override;
+
   /// GetInstSize - Return the number of bytes of code the specified
   /// instruction may be.  This returns the maximum number of bytes.
   ///
   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
   void getNoop(MCInst &NopInst) const override;
 
   std::pair<unsigned, unsigned>

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

unsigned PPCInstrInfo::reduceLoopCount(
   // Since BDZ/BDZ8 that we will insert will also decrease the ctr by 1,
   // so we don't need to generate any thing here.
   Cond.push_back(MachineOperand::CreateImm(0));
   Cond.push_back(MachineOperand::CreateReg(
       Subtarget.isPPC64() ? PPC::CTR8 : PPC::CTR, true));
   return LoopCountReg;
 }
 
+// Return true if get the base operand, byte offset of an instruction and the
+// memory width. Width is the size of memory that is being loaded/stored.
+bool PPCInstrInfo::getMemOperandWithOffsetWidth(
+  const MachineInstr &LdSt,
+  const MachineOperand *&BaseReg,
+  int64_t &Offset,
+  unsigned &Width,
+  const TargetRegisterInfo *TRI) const {
+  assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
+
+  // Handle only loads/stores with base register followed by immediate offset.
+  if (LdSt.getNumExplicitOperands() != 3)
+    return false;
+  if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
+    return false;
+
+  if (!LdSt.hasOneMemOperand())
+    return false;
+
+  Width = (*LdSt.memoperands_begin())->getSize();
+  Offset = LdSt.getOperand(1).getImm();
+  BaseReg = &LdSt.getOperand(2);
+  return true;
+}
+
+bool PPCInstrInfo::areMemAccessesTriviallyDisjoint(
+    const MachineInstr &MIa, const MachineInstr &MIb,
+    AliasAnalysis * /*AA*/) const {
+  assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
+  assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
+
+  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
+      MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
+    return false;
+
+  // Retrieve the base register, offset from the base register and width. Width
+  // is the size of memory that is being loaded/stored (e.g. 1, 2, 4).  If
+  // base registers are identical, and the offset of a lower memory access +
+  // the width doesn't overlap the offset of a higher memory access,
+  // then the memory accesses are different.
+  const TargetRegisterInfo *TRI = &getRegisterInfo();
+  const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
+  int64_t OffsetA = 0, OffsetB = 0;
+  unsigned int WidthA = 0, WidthB = 0;
+  if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
+      getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
+    if (BaseOpA->isIdenticalTo(*BaseOpB)) {
+      int LowOffset = std::min(OffsetA, OffsetB);
+      int HighOffset = std::max(OffsetA, OffsetB);
+      int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
+      if (LowOffset + LowWidth <= HighOffset)
+        return true;
+    }
+  }
+  return false;
+}

llvm/trunk/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s
 
 define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
 ; CHECK-LABEL: __fixunstfdi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -464(1)
 ; CHECK-NEXT:    mfcr 12
 ; CHECK-NEXT:    stw 29, 412(1) # 4-byte Folded Spill
 ; CHECK-NEXT:    stw 30, 416(1) # 4-byte Folded Spill
 ; CHECK-NEXT:    lis 3, .LCPI0_0@ha
 ; CHECK-NEXT:    stw 12, 408(1)
+; CHECK-NEXT:    stfd 2, 376(1)
 ; CHECK-NEXT:    stfd 27, 424(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stfd 1, 384(1)
 ; CHECK-NEXT:    stfd 28, 432(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd 29, 440(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd 30, 448(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd 31, 456(1) # 8-byte Folded Spill
-; CHECK-NEXT:    stfd 2, 376(1)
-; CHECK-NEXT:    lfs 27, .LCPI0_0@l(3)
-; CHECK-NEXT:    stfd 1, 384(1)
 ; CHECK-NEXT:    lwz 4, 380(1)
+; CHECK-NEXT:    lfs 27, .LCPI0_0@l(3)
+; CHECK-NEXT:    lwz 3, 384(1)
+; CHECK-NEXT:    stw 4, 396(1)
 ; CHECK-NEXT:    fcmpu 0, 2, 27
+; CHECK-NEXT:    lwz 4, 376(1)
 ; CHECK-NEXT:    fcmpu 1, 1, 27
 ; CHECK-NEXT:    crand 20, 6, 0
-; CHECK-NEXT:    stw 4, 396(1)
 ; CHECK-NEXT:    cror 20, 4, 20
-; CHECK-NEXT:    lwz 4, 376(1)
 ; CHECK-NEXT:    stw 4, 392(1)
+; CHECK-NEXT:    stw 3, 400(1)
 ; CHECK-NEXT:    lwz 4, 388(1)
 ; CHECK-NEXT:    stw 4, 404(1)
-; CHECK-NEXT:    lwz 3, 384(1)
-; CHECK-NEXT:    stw 3, 400(1)
 ; CHECK-NEXT:    bc 4, 20, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %bb5
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    b .LBB0_16
 ; CHECK-NEXT:  .LBB0_2: # %bb1
 ; CHECK-NEXT:    lfd 0, 400(1)
+; CHECK-NEXT:    lis 3, 15856
+; CHECK-NEXT:    stw 3, 336(1)
 ; CHECK-NEXT:    lfd 1, 392(1)
 ; CHECK-NEXT:    li 29, 0
-; CHECK-NEXT:    lis 3, 15856
 ; CHECK-NEXT:    stfd 0, 304(1)
-; CHECK-NEXT:    stfd 1, 296(1)
 ; CHECK-NEXT:    stw 29, 340(1)
-; CHECK-NEXT:    stw 3, 336(1)
 ; CHECK-NEXT:    stw 29, 332(1)
 ; CHECK-NEXT:    stw 29, 328(1)
 ; CHECK-NEXT:    lwz 3, 308(1)
+; CHECK-NEXT:    stfd 1, 296(1)
+; CHECK-NEXT:    lfd 3, 336(1)
+; CHECK-NEXT:    lfd 4, 328(1)
 ; CHECK-NEXT:    stw 3, 324(1)
 ; CHECK-NEXT:    lwz 3, 304(1)
 ; CHECK-NEXT:    stw 3, 320(1)
 ; CHECK-NEXT:    lwz 3, 300(1)
+; CHECK-NEXT:    lfd 31, 320(1)
 ; CHECK-NEXT:    stw 3, 316(1)
+; CHECK-NEXT:    fmr 1, 31
 ; CHECK-NEXT:    lwz 3, 296(1)
 ; CHECK-NEXT:    stw 3, 312(1)
-; CHECK-NEXT:    lfd 31, 320(1)
 ; CHECK-NEXT:    lfd 30, 312(1)
-; CHECK-NEXT:    lfd 3, 336(1)
-; CHECK-NEXT:    lfd 4, 328(1)
-; CHECK-NEXT:    fmr 1, 31
 ; CHECK-NEXT:    fmr 2, 30
 ; CHECK-NEXT:    bl __gcc_qmul@PLT
 ; CHECK-NEXT:    lis 3, 16864
 ; CHECK-NEXT:    stfd 1, 280(1)
-; CHECK-NEXT:    fmr 29, 1
+; CHECK-NEXT:    stw 3, 368(1)
 ; CHECK-NEXT:    stfd 2, 288(1)
-; CHECK-NEXT:    fmr 28, 2
 ; CHECK-NEXT:    stw 29, 372(1)
-; CHECK-NEXT:    stw 3, 368(1)
 ; CHECK-NEXT:    stw 29, 364(1)
 ; CHECK-NEXT:    stw 29, 360(1)
+; CHECK-NEXT:    fmr 29, 1
 ; CHECK-NEXT:    lwz 3, 284(1)
+; CHECK-NEXT:    fmr 28, 2
+; CHECK-NEXT:    lfd 3, 368(1)
+; CHECK-NEXT:    lfd 4, 360(1)
 ; CHECK-NEXT:    stw 3, 356(1)
 ; CHECK-NEXT:    lwz 3, 280(1)
 ; CHECK-NEXT:    stw 3, 352(1)
 ; CHECK-NEXT:    lwz 3, 292(1)
+; CHECK-NEXT:    lfd 1, 352(1)
 ; CHECK-NEXT:    stw 3, 348(1)
 ; CHECK-NEXT:    lwz 3, 288(1)
 ; CHECK-NEXT:    stw 3, 344(1)
-; CHECK-NEXT:    lfd 3, 368(1)
-; CHECK-NEXT:    lfd 4, 360(1)
-; CHECK-NEXT:    lfd 1, 352(1)
 ; CHECK-NEXT:    lfd 2, 344(1)
 ; CHECK-NEXT:    bl __gcc_qsub@PLT
 ; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    lis 3, .LCPI0_1@ha
 ; CHECK-NEXT:    fcmpu 0, 28, 27
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 1, 2, 1
 ; CHECK-NEXT:    mtfsf 1, 0
 ; CHECK-NEXT:    fctiwz 0, 1
 ; CHECK-NEXT:    mffs 1
 ; CHECK-NEXT:    stfd 0, 160(1)
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 0, 28, 29
 ; CHECK-NEXT:    mtfsf 1, 1
 ; CHECK-NEXT:    lfs 1, .LCPI0_1@l(3)
 ; CHECK-NEXT:    fctiwz 0, 0
 ; CHECK-NEXT:    stfd 0, 152(1)
-; CHECK-NEXT:    fcmpu 1, 29, 1
 ; CHECK-NEXT:    lwz 3, 164(1)
+; CHECK-NEXT:    fcmpu 1, 29, 1
 ; CHECK-NEXT:    lwz 4, 156(1)
 ; CHECK-NEXT:    crandc 20, 6, 0
 ; CHECK-NEXT:    cror 20, 5, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_4
 ; CHECK-NEXT:  # %bb.3: # %bb1
 ; CHECK-NEXT:    ori 30, 4, 0
 ; CHECK-NEXT:    b .LBB0_5
 ; CHECK-NEXT:  .LBB0_4: # %bb1
 ; CHECK-NEXT:    addi 30, 3, 0
 ; CHECK-NEXT:  .LBB0_5: # %bb1
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    mr 3, 30
 ; CHECK-NEXT:    bl __floatditf@PLT
 ; CHECK-NEXT:    lis 3, 17392
 ; CHECK-NEXT:    stfd 1, 208(1)
-; CHECK-NEXT:    fmr 29, 1
+; CHECK-NEXT:    stw 3, 240(1)
 ; CHECK-NEXT:    stfd 2, 200(1)
-; CHECK-NEXT:    fmr 28, 2
 ; CHECK-NEXT:    stw 29, 244(1)
-; CHECK-NEXT:    stw 3, 240(1)
-; CHECK-NEXT:    cmpwi 2, 30, 0
 ; CHECK-NEXT:    stw 29, 236(1)
 ; CHECK-NEXT:    stw 29, 232(1)
+; CHECK-NEXT:    fmr 29, 1
 ; CHECK-NEXT:    lwz 3, 212(1)
+; CHECK-NEXT:    fmr 28, 2
+; CHECK-NEXT:    lfd 3, 240(1)
+; CHECK-NEXT:    lfd 4, 232(1)
+; CHECK-NEXT:    cmpwi 2, 30, 0
 ; CHECK-NEXT:    stw 3, 228(1)
 ; CHECK-NEXT:    lwz 3, 208(1)
 ; CHECK-NEXT:    stw 3, 224(1)
 ; CHECK-NEXT:    lwz 3, 204(1)
+; CHECK-NEXT:    lfd 1, 224(1)
 ; CHECK-NEXT:    stw 3, 220(1)
 ; CHECK-NEXT:    lwz 3, 200(1)
 ; CHECK-NEXT:    stw 3, 216(1)
-; CHECK-NEXT:    lfd 3, 240(1)
-; CHECK-NEXT:    lfd 4, 232(1)
-; CHECK-NEXT:    lfd 1, 224(1)
 ; CHECK-NEXT:    lfd 2, 216(1)
 ; CHECK-NEXT:    bl __gcc_qadd@PLT
 ; CHECK-NEXT:    blt 2, .LBB0_7
 ; CHECK-NEXT:  # %bb.6: # %bb1
 ; CHECK-NEXT:    fmr 2, 28
 ; CHECK-NEXT:  .LBB0_7: # %bb1
 ; CHECK-NEXT:    blt 2, .LBB0_9
 ; CHECK-NEXT:  # %bb.8: # %bb1
 ; CHECK-NEXT:    fmr 1, 29
 ; CHECK-NEXT:  .LBB0_9: # %bb1
 ; CHECK-NEXT:    stfd 1, 184(1)
-; CHECK-NEXT:    fmr 1, 31
 ; CHECK-NEXT:    stfd 2, 192(1)
-; CHECK-NEXT:    fmr 2, 30
+; CHECK-NEXT:    fmr 1, 31
 ; CHECK-NEXT:    lwz 3, 188(1)
+; CHECK-NEXT:    fmr 2, 30
 ; CHECK-NEXT:    stw 3, 260(1)
 ; CHECK-NEXT:    lwz 3, 184(1)
 ; CHECK-NEXT:    stw 3, 256(1)
 ; CHECK-NEXT:    lwz 3, 196(1)
+; CHECK-NEXT:    lfd 3, 256(1)
 ; CHECK-NEXT:    stw 3, 252(1)
 ; CHECK-NEXT:    lwz 3, 192(1)
 ; CHECK-NEXT:    stw 3, 248(1)
-; CHECK-NEXT:    lfd 3, 256(1)
 ; CHECK-NEXT:    lfd 4, 248(1)
 ; CHECK-NEXT:    bl __gcc_qsub@PLT
 ; CHECK-NEXT:    stfd 2, 176(1)
-; CHECK-NEXT:    fcmpu 0, 2, 27
 ; CHECK-NEXT:    stfd 1, 168(1)
-; CHECK-NEXT:    fcmpu 1, 1, 27
+; CHECK-NEXT:    fcmpu 0, 2, 27
 ; CHECK-NEXT:    lwz 3, 180(1)
+; CHECK-NEXT:    fcmpu 1, 1, 27
 ; CHECK-NEXT:    crandc 20, 6, 0
 ; CHECK-NEXT:    cror 21, 5, 7
-; CHECK-NEXT:    cror 20, 21, 20
 ; CHECK-NEXT:    stw 3, 268(1)
+; CHECK-NEXT:    cror 20, 21, 20
 ; CHECK-NEXT:    lwz 3, 176(1)
 ; CHECK-NEXT:    stw 3, 264(1)
 ; CHECK-NEXT:    lwz 3, 172(1)
+; CHECK-NEXT:    lfd 30, 264(1)
 ; CHECK-NEXT:    stw 3, 276(1)
 ; CHECK-NEXT:    lwz 3, 168(1)
 ; CHECK-NEXT:    stw 3, 272(1)
-; CHECK-NEXT:    lfd 30, 264(1)
 ; CHECK-NEXT:    lfd 31, 272(1)
 ; CHECK-NEXT:    bc 12, 20, .LBB0_13
 ; CHECK-NEXT:  # %bb.10: # %bb2
-; CHECK-NEXT:    fneg 29, 30
 ; CHECK-NEXT:    fneg 28, 31
-; CHECK-NEXT:    li 29, 0
-; CHECK-NEXT:    lis 3, 16864
 ; CHECK-NEXT:    stfd 28, 48(1)
+; CHECK-NEXT:    lis 3, 16864
+; CHECK-NEXT:    stw 3, 80(1)
+; CHECK-NEXT:    fneg 29, 30
+; CHECK-NEXT:    lwz 3, 52(1)
 ; CHECK-NEXT:    stfd 29, 40(1)
+; CHECK-NEXT:    li 29, 0
 ; CHECK-NEXT:    stw 29, 84(1)
-; CHECK-NEXT:    stw 3, 80(1)
 ; CHECK-NEXT:    stw 29, 76(1)
 ; CHECK-NEXT:    stw 29, 72(1)
-; CHECK-NEXT:    lwz 3, 52(1)
 ; CHECK-NEXT:    stw 3, 68(1)
+; CHECK-NEXT:    lfd 3, 80(1)
+; CHECK-NEXT:    lfd 4, 72(1)
 ; CHECK-NEXT:    lwz 3, 48(1)
 ; CHECK-NEXT:    stw 3, 64(1)
 ; CHECK-NEXT:    lwz 3, 44(1)
+; CHECK-NEXT:    lfd 1, 64(1)
 ; CHECK-NEXT:    stw 3, 60(1)
 ; CHECK-NEXT:    lwz 3, 40(1)
 ; CHECK-NEXT:    stw 3, 56(1)
-; CHECK-NEXT:    lfd 3, 80(1)
-; CHECK-NEXT:    lfd 4, 72(1)
-; CHECK-NEXT:    lfd 1, 64(1)
 ; CHECK-NEXT:    lfd 2, 56(1)
 ; CHECK-NEXT:    bl __gcc_qsub@PLT
 ; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    lis 3, .LCPI0_2@ha
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 1, 2, 1
 ; CHECK-NEXT:    mtfsf 1, 0
 ; CHECK-NEXT:    fctiwz 0, 1
 ; CHECK-NEXT:    mffs 1
 ; CHECK-NEXT:    stfd 0, 32(1)
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    lfs 0, .LCPI0_2@l(3)
 ; CHECK-NEXT:    lis 3, .LCPI0_3@ha
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 2, 29, 28
 ; CHECK-NEXT:    mtfsf 1, 1
 ; CHECK-NEXT:    lfs 1, .LCPI0_3@l(3)
 ; CHECK-NEXT:    fcmpu 0, 30, 0
 ; CHECK-NEXT:    fctiwz 2, 2
 ; CHECK-NEXT:    stfd 2, 24(1)
-; CHECK-NEXT:    fcmpu 1, 31, 1
 ; CHECK-NEXT:    lwz 3, 36(1)
+; CHECK-NEXT:    fcmpu 1, 31, 1
 ; CHECK-NEXT:    lwz 4, 28(1)
 ; CHECK-NEXT:    crandc 20, 6, 1
 ; CHECK-NEXT:    cror 20, 4, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_12
 ; CHECK-NEXT:  # %bb.11: # %bb2
 ; CHECK-NEXT:    ori 3, 4, 0
 ; CHECK-NEXT:    b .LBB0_12
 ; CHECK-NEXT:  .LBB0_12: # %bb2
 ; CHECK-NEXT:    subfic 4, 3, 0
 ; CHECK-NEXT:    subfe 3, 29, 30
 ; CHECK-NEXT:    b .LBB0_16
 ; CHECK-NEXT:  .LBB0_13: # %bb3
-; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    lis 4, 16864
 ; CHECK-NEXT:    stfd 31, 112(1)
-; CHECK-NEXT:    stfd 30, 104(1)
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    stw 3, 148(1)
-; CHECK-NEXT:    stw 4, 144(1)
 ; CHECK-NEXT:    stw 3, 140(1)
 ; CHECK-NEXT:    stw 3, 136(1)
+; CHECK-NEXT:    stfd 30, 104(1)
+; CHECK-NEXT:    lis 4, 16864
 ; CHECK-NEXT:    lwz 3, 116(1)
+; CHECK-NEXT:    stw 4, 144(1)
+; CHECK-NEXT:    lfd 4, 136(1)
 ; CHECK-NEXT:    stw 3, 132(1)
+; CHECK-NEXT:    lfd 3, 144(1)
 ; CHECK-NEXT:    lwz 3, 112(1)
 ; CHECK-NEXT:    stw 3, 128(1)
 ; CHECK-NEXT:    lwz 3, 108(1)
+; CHECK-NEXT:    lfd 1, 128(1)
 ; CHECK-NEXT:    stw 3, 124(1)
 ; CHECK-NEXT:    lwz 3, 104(1)
 ; CHECK-NEXT:    stw 3, 120(1)
-; CHECK-NEXT:    lfd 3, 144(1)
-; CHECK-NEXT:    lfd 4, 136(1)
-; CHECK-NEXT:    lfd 1, 128(1)
 ; CHECK-NEXT:    lfd 2, 120(1)
 ; CHECK-NEXT:    bl __gcc_qsub@PLT
 ; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    lis 3, .LCPI0_0@ha
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 1, 2, 1
 ; CHECK-NEXT:    mtfsf 1, 0
 ; CHECK-NEXT:    fctiwz 0, 1
 ; CHECK-NEXT:    mffs 1
 ; CHECK-NEXT:    stfd 0, 96(1)
 ; CHECK-NEXT:    mtfsb1 31
 ; CHECK-NEXT:    lfs 0, .LCPI0_0@l(3)
 ; CHECK-NEXT:    lis 3, .LCPI0_1@ha
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 2, 30, 31
 ; CHECK-NEXT:    mtfsf 1, 1
 ; CHECK-NEXT:    lfs 1, .LCPI0_1@l(3)
 ; CHECK-NEXT:    fcmpu 0, 30, 0
 ; CHECK-NEXT:    fctiwz 2, 2
 ; CHECK-NEXT:    stfd 2, 88(1)
-; CHECK-NEXT:    fcmpu 1, 31, 1
 ; CHECK-NEXT:    lwz 3, 100(1)
+; CHECK-NEXT:    fcmpu 1, 31, 1
 ; CHECK-NEXT:    lwz 4, 92(1)
 ; CHECK-NEXT:    crandc 20, 6, 0
 ; CHECK-NEXT:    cror 20, 5, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_14
 ; CHECK-NEXT:    b .LBB0_15
 ; CHECK-NEXT:  .LBB0_14: # %bb3
 ; CHECK-NEXT:    addi 4, 3, 0

llvm/trunk/test/CodeGen/PowerPC/extract-and-store.ll

 ; CHECK-NEXT:    rldicl r6, r3, 24, 56
 ; CHECK-NEXT:    stb r4, 6(r5)
 ; CHECK-NEXT:    rldicl r4, r3, 8, 56
 ; CHECK-NEXT:    stb r6, 7(r5)
 ; CHECK-NEXT:    rldicl r3, r3, 16, 56
 ; CHECK-NEXT:    stb r4, 9(r5)
 ; CHECK-NEXT:    rldicl r4, r7, 32, 56
 ; CHECK-NEXT:    rldicl r6, r7, 8, 56
+; CHECK-NEXT:    stb r3, 12(r5)
 ; CHECK-NEXT:    stb r4, 0(r5)
 ; CHECK-NEXT:    rldicl r4, r7, 16, 56
 ; CHECK-NEXT:    stb r6, 3(r5)
 ; CHECK-NEXT:    clrldi r6, r7, 56
 ; CHECK-NEXT:    stb r4, 4(r5)
 ; CHECK-NEXT:    rldicl r4, r7, 48, 56
 ; CHECK-NEXT:    stb r6, 5(r5)
 ; CHECK-NEXT:    rldicl r6, r7, 56, 56
 ; CHECK-NEXT:    stb r4, 8(r5)
 ; CHECK-NEXT:    rldicl r4, r7, 24, 56
 ; CHECK-NEXT:    stb r6, 10(r5)
 ; CHECK-NEXT:    stb r4, 11(r5)
-; CHECK-NEXT:    stb r3, 12(r5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_13_consecutive_stores_of_bytes:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mfvsrd r3, vs34
 ; CHECK-BE-NEXT:    xxswapd vs0, vs34
 ; CHECK-BE-NEXT:    rldicl r4, r3, 40, 56
 ; CHECK-BE-NEXT:    clrldi r6, r3, 56

llvm/trunk/test/CodeGen/PowerPC/f128-aggregates.ll

 
 ; Since we can only pass a max of 8 float128 value in VSX registers, ensure we
 ; store to stack if passing more.
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly
                             align 16 %a) {
 ; CHECK-LABEL: testStruct_03:
 ; CHECK:       # %bb.0: # %entry
+; CHECK:        lxv v2, 128(r1)
 ; CHECK-DAG:    std r10, 88(r1)
 ; CHECK-DAG:    std r9, 80(r1)
 ; CHECK-DAG:    std r8, 72(r1)
 ; CHECK-DAG:    std r7, 64(r1)
 ; CHECK-DAG:    std r6, 56(r1)
 ; CHECK-DAG:    std r5, 48(r1)
 ; CHECK-DAG:    std r4, 40(r1)
 ; CHECK-DAG:    std r3, 32(r1)
-; CHECK-NEXT:    lxv v2, 128(r1)
 ; CHECK-NEXT:    blr
 
 ; CHECK-BE-LABEL: testStruct_03:
 ; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE:        lxv v2, 144(r1)
 ; CHECK-BE-DAG:    std r10, 104(r1)
 ; CHECK-BE-DAG:    std r9, 96(r1)
 ; CHECK-BE-DAG:    std r8, 88(r1)
 ; CHECK-BE-DAG:    std r7, 80(r1)
 ; CHECK-BE-DAG:    std r6, 72(r1)
 ; CHECK-BE-DAG:    std r5, 64(r1)
 ; CHECK-BE-DAG:    std r4, 56(r1)
 ; CHECK-BE-DAG:    std r3, 48(r1)
-; CHECK-BE-NEXT:    lxv v2, 144(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a7 = getelementptr inbounds %struct.With9fp128params,
                                %struct.With9fp128params* %a, i64 0, i32 6
   %0 = load fp128, fp128* %a7, align 16
   ret fp128 %0
 }
 
entry:
   ret fp128 %add3
 }
 
 
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) {
 ; CHECK-LABEL: testNestedAggregate:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-DAG:     std r10, 88(r1)
-; CHECK-DAG:     std r9, 80(r1)
 ; CHECK-DAG:     std r8, 72(r1)
 ; CHECK-DAG:     std r7, 64(r1)
+; CHECK:         lxv v2, 64(r1)
+; CHECK-DAG:     std r10, 88(r1)
+; CHECK-DAG:     std r9, 80(r1)
 ; CHECK-DAG:     std r6, 56(r1)
 ; CHECK-DAG:     std r5, 48(r1)
 ; CHECK-DAG:     std r4, 40(r1)
 ; CHECK-DAG:     std r3, 32(r1)
-; CHECK-NEXT:    lxv v2, 64(r1)
 ; CHECK-NEXT:    blr
 
 ; CHECK-BE-LABEL: testNestedAggregate:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-DAG:     std r8, 88(r1)
 ; CHECK-BE-DAG:     std r7, 80(r1)
+; CHECK-BE-NEXT:    lxv v2, 80(r1)
 ; CHECK-BE-DAG:     std r10, 104(r1)
 ; CHECK-BE-DAG:     std r9, 96(r1)
 ; CHECK-BE-DAG:     std r6, 72(r1)
 ; CHECK-BE-DAG:     std r5, 64(r1)
 ; CHECK-BE-DAG:     std r4, 56(r1)
 ; CHECK-BE-DAG:     std r3, 48(r1)
-; CHECK-BE-NEXT:    lxv v2, 80(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
   %0 = load fp128, fp128* %c, align 16
   ret fp128 %0
 }
 
 ; Function Attrs: norecurse nounwind readnone

llvm/trunk/test/CodeGen/PowerPC/legalize-vaarg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;RUN: llc < %s --mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=BE
 ;RUN: llc < %s --mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=LE
 
 define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
 ; BE-LABEL: test_large_vec_vaarg:
 ; BE:       # %bb.0:
+; BE-NEXT:    ld 3, -8(1)
 ; BE-NEXT:    std 4, 56(1)
 ; BE-NEXT:    std 5, 64(1)
 ; BE-NEXT:    std 6, 72(1)
 ; BE-NEXT:    std 7, 80(1)
 ; BE-NEXT:    std 8, 88(1)
 ; BE-NEXT:    std 9, 96(1)
 ; BE-NEXT:    std 10, 104(1)
-; BE-NEXT:    ld 3, -8(1)
 ; BE-NEXT:    addi 3, 3, 15
 ; BE-NEXT:    rldicr 3, 3, 0, 59
 ; BE-NEXT:    addi 4, 3, 16
 ; BE-NEXT:    addi 5, 3, 31
 ; BE-NEXT:    std 4, -8(1)
 ; BE-NEXT:    rldicr 4, 5, 0, 59
 ; BE-NEXT:    lvx 2, 0, 3
 ; BE-NEXT:    addi 3, 4, 16
 ; BE-NEXT:    std 3, -8(1)
 ; BE-NEXT:    lvx 3, 0, 4
 ; BE-NEXT:    blr
 ;
 ; LE-LABEL: test_large_vec_vaarg:
 ; LE:       # %bb.0:
+; LE-NEXT:    ld 3, -8(1)
 ; LE-NEXT:    std 4, 40(1)
 ; LE-NEXT:    std 5, 48(1)
 ; LE-NEXT:    std 6, 56(1)
 ; LE-NEXT:    std 7, 64(1)
+; LE-NEXT:    addi 3, 3, 15
+; LE-NEXT:    rldicr 3, 3, 0, 59
 ; LE-NEXT:    std 8, 72(1)
 ; LE-NEXT:    std 9, 80(1)
 ; LE-NEXT:    std 10, 88(1)
-; LE-NEXT:    ld 3, -8(1)
-; LE-NEXT:    addi 3, 3, 15
-; LE-NEXT:    rldicr 3, 3, 0, 59
 ; LE-NEXT:    addi 4, 3, 31
 ; LE-NEXT:    addi 5, 3, 16
 ; LE-NEXT:    rldicr 4, 4, 0, 59
 ; LE-NEXT:    std 5, -8(1)
 ; LE-NEXT:    addi 5, 4, 16
 ; LE-NEXT:    lvx 2, 0, 3
 ; LE-NEXT:    std 5, -8(1)
 ; LE-NEXT:    lvx 3, 0, 4
 ; LE-NEXT:    blr
   %args = alloca i8*, align 4
   %x = va_arg i8** %args, <8 x i32>
   ret <8 x i32> %x
 }

llvm/trunk/test/CodeGen/PowerPC/ppc32-skip-regs.ll

entry:
   %0 = load ppc_fp128, ppc_fp128* @x, align 16
   %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), ppc_fp128 %0, ppc_fp128 %0)
   ret void
 }
 ; Do not put second argument of function in r8 register, because there is no enough registers
 ; left for long double type (4 registers in soft float mode). Instead in r8 register this
 ; argument put on stack.
 ; CHECK-NOT: mr 8, 4
-; CHECK: stw 7, 20(1)
 ; CHECK: stw 6, 16(1)
 ; CHECK: stw 5, 12(1)
 ; CHECK: stw 4, 8(1)
+; CHECK: stw 7, 20(1)
 
 declare i32 @printf(i8* nocapture readonly, ...)
 
 attributes #0 = { "use-soft-float"="true" }

llvm/trunk/test/CodeGen/PowerPC/scheduling-mem-dependency.ll

+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
+define i64 @store_disjoint_memory(i64* nocapture %P, i64 %v) {
+entry:
+; CHECK: ********** MI Scheduling **********
+; CHECK-LABEL: store_disjoint_memory:%bb.0
+; CHECK:SU(2):   STD renamable $x4, 24, renamable $x5 :: (store 8 into %ir.arrayidx)
+; CHECK-NOT: Successors:
+; CHECK-NOT:    SU(3): Ord  Latency=0 Memory
+; CHECK:SU(3):   STD renamable $x4, 16, renamable $x5 :: (store 8 into %ir.arrayidx1)
+; CHECK: Predecessors:
+; CHECK-NOT:    SU(2): Ord  Latency=0 Memory
+  %arrayidx = getelementptr inbounds i64, i64* %P, i64 3
+  store i64 %v, i64* %arrayidx
+  %arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
+  store i64 %v, i64* %arrayidx1
+  ret i64 %v
+}

llvm/trunk/test/CodeGen/PowerPC/varargs.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck -check-prefix=P32 %s
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck -check-prefix=P64 %s
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefix=P64 %s
 
 ; PR8327
 define i8* @test1(i8** %foo) nounwind {
 ; P32-LABEL: test1:
 ; P32:       # %bb.0:
 ; P32-NEXT:    lbz r4, 0(r3)
-; P32-NEXT:    addi r5, r4, 1
-; P32-NEXT:    stb r5, 0(r3)
-; P32-NEXT:    cmpwi r4, 8
 ; P32-NEXT:    lwz r5, 4(r3)
+; P32-NEXT:    lwz r6, 8(r3)
+; P32-NEXT:    addi r7, r4, 1
+; P32-NEXT:    stb r7, 0(r3)
+; P32-NEXT:    addi r7, r5, 4
+; P32-NEXT:    cmpwi r4, 8
 ; P32-NEXT:    slwi r4, r4, 2
-; P32-NEXT:    addi r6, r5, 4
-; P32-NEXT:    bc 12, lt, .LBB0_1
-; P32-NEXT:    b .LBB0_2
-; P32-NEXT:  .LBB0_1:
-; P32-NEXT:    addi r6, r5, 0
+; P32-NEXT:    add r4, r6, r4
+; P32-NEXT:    bc 12, lt, .LBB0_2
+; P32-NEXT:  # %bb.1:
+; P32-NEXT:    ori r6, r7, 0
+; P32-NEXT:    b .LBB0_3
 ; P32-NEXT:  .LBB0_2:
+; P32-NEXT:    addi r6, r5, 0
+; P32-NEXT:  .LBB0_3:
 ; P32-NEXT:    stw r6, 4(r3)
-; P32-NEXT:    lwz r3, 8(r3)
-; P32-NEXT:    add r3, r3, r4
-; P32-NEXT:    bc 12, lt, .LBB0_4
-; P32-NEXT:  # %bb.3:
+; P32-NEXT:    bc 12, lt, .LBB0_5
+; P32-NEXT:  # %bb.4:
 ; P32-NEXT:    ori r3, r5, 0
-; P32-NEXT:    b .LBB0_4
-; P32-NEXT:  .LBB0_4:
+; P32-NEXT:    b .LBB0_6
+; P32-NEXT:  .LBB0_5:
+; P32-NEXT:    addi r3, r4, 0
+; P32-NEXT:  .LBB0_6:
 ; P32-NEXT:    lwz r3, 0(r3)
 ; P32-NEXT:    blr
 ;
 ; P64-LABEL: test1:
 ; P64:       # %bb.0:
 ; P64-NEXT:    ld r4, 0(r3)
 ; P64-NEXT:    addi r5, r4, 8
 ; P64-NEXT:    std r5, 0(r3)
 ; P64-NEXT:    ld r3, 0(r4)
 ; P64-NEXT:    blr
   %A = va_arg i8** %foo, i8*
   ret i8* %A
 }
 
 

llvm/trunk/test/CodeGen/PowerPC/vec-min-max.ll

 ; NOP8VEC-NEXT:    xxswapd 0, 35
 ; NOP8VEC-NEXT:    addi 3, 1, -32
 ; NOP8VEC-NEXT:    addi 4, 1, -48
 ; NOP8VEC-NEXT:    xxswapd 1, 34
 ; NOP8VEC-NEXT:    stxvd2x 0, 0, 3
 ; NOP8VEC-NEXT:    stxvd2x 1, 0, 4
 ; NOP8VEC-NEXT:    ld 3, -24(1)
 ; NOP8VEC-NEXT:    ld 4, -40(1)
+; NOP8VEC-NEXT:    ld 6, -48(1)
 ; NOP8VEC-NEXT:    cmpd 4, 3
 ; NOP8VEC-NEXT:    li 3, 0
 ; NOP8VEC-NEXT:    li 4, -1
 ; NOP8VEC-NEXT:    isel 5, 4, 3, 1
 ; NOP8VEC-NEXT:    std 5, -8(1)
 ; NOP8VEC-NEXT:    ld 5, -32(1)
-; NOP8VEC-NEXT:    ld 6, -48(1)
 ; NOP8VEC-NEXT:    cmpd 6, 5
 ; NOP8VEC-NEXT:    isel 3, 4, 3, 1
 ; NOP8VEC-NEXT:    std 3, -16(1)
 ; NOP8VEC-NEXT:    addi 3, 1, -16
 ; NOP8VEC-NEXT:    lxvd2x 0, 0, 3
 ; NOP8VEC-NEXT:    xxswapd 36, 0
 ; NOP8VEC-NEXT:    xxsel 34, 35, 34, 36
 ; NOP8VEC-NEXT:    blr

 ; NOP8VEC-NEXT:    xxswapd 0, 35
 ; NOP8VEC-NEXT:    addi 3, 1, -32
 ; NOP8VEC-NEXT:    addi 4, 1, -48
 ; NOP8VEC-NEXT:    xxswapd 1, 34
 ; NOP8VEC-NEXT:    stxvd2x 0, 0, 3
 ; NOP8VEC-NEXT:    stxvd2x 1, 0, 4
 ; NOP8VEC-NEXT:    ld 3, -24(1)
 ; NOP8VEC-NEXT:    ld 4, -40(1)
+; NOP8VEC-NEXT:    ld 6, -48(1)
 ; NOP8VEC-NEXT:    cmpd 4, 3
 ; NOP8VEC-NEXT:    li 3, 0
 ; NOP8VEC-NEXT:    li 4, -1
 ; NOP8VEC-NEXT:    isel 5, 4, 3, 0
 ; NOP8VEC-NEXT:    std 5, -8(1)
 ; NOP8VEC-NEXT:    ld 5, -32(1)
-; NOP8VEC-NEXT:    ld 6, -48(1)
 ; NOP8VEC-NEXT:    cmpd 6, 5
 ; NOP8VEC-NEXT:    isel 3, 4, 3, 0
 ; NOP8VEC-NEXT:    std 3, -16(1)
 ; NOP8VEC-NEXT:    addi 3, 1, -16
 ; NOP8VEC-NEXT:    lxvd2x 0, 0, 3
 ; NOP8VEC-NEXT:    xxswapd 36, 0
 ; NOP8VEC-NEXT:    xxsel 34, 35, 34, 36
 ; NOP8VEC-NEXT:    blr

llvm/trunk/test/CodeGen/PowerPC/vsx.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    add r3, r4, r3
+; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    ld r3, -32(r1)
-; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test26:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    add r3, r4, r3
+; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    ld r3, -32(r1)
-; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    add r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test26:
 ; CHECK-FISL:       # %bb.0:

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-NEXT:    lwz r3, -20(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    sld r3, r4, r3
+; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lwz r3, -28(r1)
-; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    sld r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test60:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-REG-NEXT:    lwz r3, -20(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    sld r3, r4, r3
+; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lwz r3, -28(r1)
-; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    sld r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test60:
 ; CHECK-FISL:       # %bb.0:

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-NEXT:    lwz r3, -20(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    srd r3, r4, r3
+; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lwz r3, -28(r1)
-; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    srd r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test61:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-REG-NEXT:    lwz r3, -20(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    srd r3, r4, r3
+; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lwz r3, -28(r1)
-; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    srd r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test61:
 ; CHECK-FISL:       # %bb.0:

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-NEXT:    lwz r3, -20(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    srad r3, r4, r3
+; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    lwz r3, -28(r1)
-; CHECK-NEXT:    ld r4, -48(r1)
 ; CHECK-NEXT:    srad r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test62:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-REG-NEXT:    lwz r3, -20(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    srad r3, r4, r3
+; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    std r3, -8(r1)
 ; CHECK-REG-NEXT:    lwz r3, -28(r1)
-; CHECK-REG-NEXT:    ld r4, -48(r1)
 ; CHECK-REG-NEXT:    srad r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test62:
 ; CHECK-FISL:       # %bb.0:

 ; CHECK-LABEL: test67:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi r3, r1, -32
 ; CHECK-NEXT:    addi r4, r1, -48
 ; CHECK-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
+; CHECK-NEXT:    ld r6, -48(r1)
 ; CHECK-NEXT:    cmpld r4, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    li r4, -1
 ; CHECK-NEXT:    isel r5, r4, r3, lt
 ; CHECK-NEXT:    std r5, -8(r1)
 ; CHECK-NEXT:    ld r5, -32(r1)
-; CHECK-NEXT:    ld r6, -48(r1)
 ; CHECK-NEXT:    cmpld r6, r5
 ; CHECK-NEXT:    isel r3, r4, r3, lt
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test67:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
+; CHECK-REG-NEXT:    ld r6, -48(r1)
 ; CHECK-REG-NEXT:    cmpld r4, r3
 ; CHECK-REG-NEXT:    li r3, 0
 ; CHECK-REG-NEXT:    li r4, -1
 ; CHECK-REG-NEXT:    isel r5, r4, r3, lt
 ; CHECK-REG-NEXT:    std r5, -8(r1)
 ; CHECK-REG-NEXT:    ld r5, -32(r1)
-; CHECK-REG-NEXT:    ld r6, -48(r1)
 ; CHECK-REG-NEXT:    cmpld r6, r5
 ; CHECK-REG-NEXT:    isel r3, r4, r3, lt
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test67: