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Differential D63724

[AMDGPU] Allow any value in unused src0 field in v_nop
ClosedPublic

Authored by tpr on Jun 24 2019, 9:26 AM.

Details

Reviewers
rampitec
kzhuravl
Commits
rGd2fdb956e044: [AMDGPU] Allow any value in unused src0 field in v_nop
rL364208: [AMDGPU] Allow any value in unused src0 field in v_nop
Summary

The LLVM disassembler assumes that the unused src0 operand of v_nop is
zero. Other tools can put another value in that field, which is still
valid. This commit fixes the LLVM disassembler to recognize such an
encoding as v_nop, in the same way as we already do for s_getpc.

Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f

Diff Detail

Repository
rL LLVM

Event Timeline

tpr created this revision.Jun 24 2019, 9:26 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 24 2019, 9:26 AM
Herald added subscribers: llvm-commits, t-tye, dstuttard and 6 others. · View Herald Transcript
Harbormaster completed remote builds in B33802: Diff 206240.Jun 24 2019, 9:27 AM
tpr added reviewers: rampitec, kzhuravl.Jun 24 2019, 9:27 AM
kzhuravl accepted this revision.Jun 24 2019, 9:30 AM

LGTM

This revision is now accepted and ready to land.Jun 24 2019, 9:30 AM
rampitec accepted this revision.Jun 24 2019, 9:36 AM

LGTM

Closed by commit rL364208: [AMDGPU] Allow any value in unused src0 field in v_nop (authored by tpr). · Explain WhyJun 24 2019, 10:36 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
2 lines
test/
MC/
Disassembler/
AMDGPU/
3 lines
3 lines
3 lines

Diff 206260

llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td

//===-- VOP1Instructions.td - Vector Instruction Defintions ---------------===// //===-- VOP1Instructions.td - Vector Instruction Defintions ---------------===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VOP1 Classes // VOP1 Classes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class VOP1e <bits<8> op, VOPProfile P> : Enc32 { class VOP1e <bits<8> op, VOPProfile P> : Enc32 {
bits<8> vdst; bits<8> vdst;
bits<9> src0; bits<9> src0;
let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, 0); let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, ?);
let Inst{16-9} = op; let Inst{16-9} = op;
let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0); let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
let Inst{31-25} = 0x3f; //encoding let Inst{31-25} = 0x3f; //encoding
} }
class VOP1_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> { class VOP1_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
bits<8> vdst; bits<8> vdst;
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llvm/trunk/test/MC/Disassembler/AMDGPU/nop.txt

# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s
# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] # CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x00 0x00 0x00 0x7e 0x00 0x00 0x00 0x7e
# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x80 0x00 0x00 0x7e

llvm/trunk/test/MC/Disassembler/AMDGPU/vop1.txt

# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s
# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] # CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x00 0x00 0x00 0x7e 0x00 0x00 0x00 0x7e
# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x80 0x00 0x00 0x7e
# CHECK: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e] # CHECK: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
0x00 0x6a 0x00 0x7e 0x00 0x6a 0x00 0x7e
# CHECK: v_mov_b32_e32 v2, v1 ; encoding: [0x01,0x03,0x04,0x7e] # CHECK: v_mov_b32_e32 v2, v1 ; encoding: [0x01,0x03,0x04,0x7e]
0x01 0x03 0x04 0x7e 0x01 0x03 0x04 0x7e
# CHECK: v_mov_b32_e32 v1, 0.5 ; encoding: [0xf0,0x02,0x02,0x7e] # CHECK: v_mov_b32_e32 v1, 0.5 ; encoding: [0xf0,0x02,0x02,0x7e]
0xf0 0x02 0x02 0x7e 0xf0 0x02 0x02 0x7e
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llvm/trunk/test/MC/Disassembler/AMDGPU/vop1_vi.txt

# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
# VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e] # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
0x02 0x03 0x02 0x7e 0x02 0x03 0x02 0x7e
# VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e] # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x00 0x00 0x00 0x7e 0x00 0x00 0x00 0x7e
# VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x80 0x00 0x00 0x7e
# VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e] # VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
0x00 0x6a 0x00 0x7e 0x00 0x6a 0x00 0x7e
# VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e] # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
0x00 0x00 0x00 0x7e 0x00 0x00 0x00 0x7e
# VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e] # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
0x02 0x03 0x02 0x7e 0x02 0x03 0x02 0x7e
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