[PowerPC] Mark FCOPYSIGN legal for FP vectors

[nemanjai]

Summary

This was just an omission in the back end. We have had the instructions for both single and double precision for a few HW generations, but never got around to legalizing these.

[jsji]

LGTM. Thanks for fixing.

[hfinkel]

In D63634#1554238, @jsji wrote:

LGTM. Thanks for fixing.

LGTM too.

lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasVSX()) {
       setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
       setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
       setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
 
       setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
       setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
       setOperationAction(ISD::FABS, MVT::v4f32, Legal);
       setOperationAction(ISD::FABS, MVT::v2f64, Legal);
+      setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
+      setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
 
       if (Subtarget.hasDirectMove())
         setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
       setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
 
       addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
     }
 

test/CodeGen/PowerPC/vector-copysign.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
+define dso_local <2 x double> @test(<2 x double> %a, <2 x double> %b) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvcpsgndp v2, v3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b)
+  ret <2 x double> %0
+}
+
+define dso_local <4 x float> @test2(<4 x float> %a, <4 x float> %b) local_unnamed_addr {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvcpsgnsp v2, v3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b)
+  ret <4 x float> %0
+}
+
+declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>)
+declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>)