[ARM GlobalISel] Add support for s64 G_ADD and G_SUB.

[efriedma]

Summary

Teach RegisterBankInfo to use the correct register class, and tell the legalizer it's legal. Everything else just works.

The one thing that's slightly weird about this compared to SelectionDAG isel is that legalization can't distinguish between i64 and <1 x i64>, so we might end up with more NEON instructions than the user expects.

(I'm not planning on spending more time on ARM 32-bit GISel at the moment; this was just a short experiment to familiarize myself with the code.)

[rovka]

LGTM, thanks!

[efriedma]

Tests committed in r363991 (https://reviews.llvm.org/rL363991)

llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp

if (ST.isThumb1Only()) {
     computeTables();
     verify(*ST.getInstrInfo());
     return;
   }
 
   getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
       .legalForCartesianProduct({s8, s16, s32}, {s1, s8, s16});
 
-  getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
+  getActionDefinitionsBuilder({G_MUL, G_AND, G_OR, G_XOR})
+      .legalFor({s32})
+      .minScalar(0, s32);
+
+  if (ST.hasNEON())
+    getActionDefinitionsBuilder({G_ADD, G_SUB})
+        .legalFor({s32, s64})
+        .minScalar(0, s32);
+  else
+    getActionDefinitionsBuilder({G_ADD, G_SUB})
         .legalFor({s32})
         .minScalar(0, s32);
 
   getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
     .legalFor({{s32, s32}})
     .minScalar(0, s32)
     .clampScalar(1, s32, s32);
 
   bool HasHWDivide = (!ST.isThumb() && ST.hasDivideInARMMode()) ||
                      (ST.isThumb() && ST.hasDivideInThumbMode());

llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp

ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 
   const MachineFunction &MF = *MI.getParent()->getParent();
   const MachineRegisterInfo &MRI = MF.getRegInfo();
   unsigned NumOperands = MI.getNumOperands();
   const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
 
   switch (Opc) {
   case G_ADD:
-  case G_SUB:
+  case G_SUB: {
+    // Integer operations where the source and destination are in the
+    // same register class.
+    LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+    OperandsMapping = Ty.getSizeInBits() == 64
+                          ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
+                          : &ARM::ValueMappings[ARM::GPR3OpsIdx];
+    break;
+  }
   case G_MUL:
   case G_AND:
   case G_OR:
   case G_XOR:
   case G_LSHR:
   case G_ASHR:
   case G_SHL:
   case G_SDIV: