GlobalISel: Ignore callsite attributes when picking intrinsic type

[arsenm]

Summary

A target intrinsic may be defined as possibly reading memory, but the
call site may have additional knowledge that it doesn't read
memory. The intrinsic lowering will expect the pessimistic assumption
of the intrinsic definition, so the chain should still be used.

I fixed the same bug in SelectionDAG in r287593.

[paquette]

LGTM

[arsenm]

r363580

lib/CodeGen/GlobalISel/IRTranslator.cpp

bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
 
   if (translateKnownIntrinsic(CI, ID, MIRBuilder))
     return true;
 
   ArrayRef<unsigned> ResultRegs;
   if (!CI.getType()->isVoidTy())
     ResultRegs = getOrCreateVRegs(CI);
 
+  // Ignore the callsite attributes. Backend code is most likely not expecting
+  // an intrinsic to sometimes have side effects and sometimes not.
   MachineInstrBuilder MIB =
-      MIRBuilder.buildIntrinsic(ID, ResultRegs, !CI.doesNotAccessMemory());
+      MIRBuilder.buildIntrinsic(ID, ResultRegs, !F->doesNotAccessMemory());
   if (isa<FPMathOperator>(CI))
     MIB->copyIRFlags(CI);
 
   for (auto &Arg : CI.arg_operands()) {
     // Some intrinsics take metadata parameters. Reject them.
     if (isa<MetadataAsValue>(Arg))
       return false;
     MIB.addUse(packRegs(*Arg, MIRBuilder));

test/CodeGen/AMDGPU/GlobalISel/irtranslator-readnone-intrinsic-callsite.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
+
+; Make sure that an intrinsic declaration that has side effects, but
+; called with a readnone call site is translated to
+; G_INTRINSIC_W_SIDE_EFFECTS
+
+; CHECK-LABEL: name: getreg_callsite_attributes
+; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg)
+; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.getreg)
+define amdgpu_kernel void @getreg_callsite_attributes() {
+  %reg0 = call i32 @llvm.amdgcn.s.getreg(i32 0)
+  store volatile i32 %reg0, i32 addrspace(1)* undef
+  %reg1 = call i32 @llvm.amdgcn.s.getreg(i32 0) #1
+  store volatile i32 %reg1, i32 addrspace(1)* undef
+  ret void
+}
+
+declare i32 @llvm.amdgcn.s.getreg(i32) #0
+
+attributes #0 = { nounwind readonly inaccessiblememonly }
+attributes #1 = { nounwind readnone }