AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1

[arsenm]

Summary

Try to fail for scc, since I don't think that should ever be produced.

[arsenm]

ping

[nhaehnle]

LGTM

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
   return selectG_ADD(I);
 }
 
 bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const {
   MachineBasicBlock *BB = I.getParent();
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
   const MachineOperand &MO = I.getOperand(0);
-  const TargetRegisterClass *RC =
-      TRI.getConstrainedRegClassForOperand(MO, MRI);
-  if (RC)
-    RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
+
+  // FIXME: Interface for getConstrainedRegClassForOperand needs work. The
+  // regbank check here is to know why getConstrainedRegClassForOperand failed.
+  const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, MRI);
+  if ((!RC && !MRI.getRegBankOrNull(MO.getReg())) ||
+      (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, MRI))) {
     I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
     return true;
   }
 
+  return false;
+}
+
 bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
   MachineBasicBlock *BB = I.getParent();
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
   unsigned SubReg = TRI.getSubRegFromChannel(I.getOperand(3).getImm() / 32);
   DebugLoc DL = I.getDebugLoc();
   MachineInstr *Ins = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG))
                                .addDef(I.getOperand(0).getReg())

lib/Target/AMDGPU/SIRegisterInfo.cpp

SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
                                          const MachineRegisterInfo &MRI) const {
   unsigned Size = getRegSizeInBits(MO.getReg(), MRI);
   const RegisterBank *RB = MRI.getRegBankOrNull(MO.getReg());
   if (!RB)
     return nullptr;
 
   Size = PowerOf2Ceil(Size);
   switch (Size) {
+  case 1: {
+    switch (RB->getID()) {
+    case AMDGPU::VGPRRegBankID:
+      return &AMDGPU::VGPR_32RegClass;
+    case AMDGPU::VCCRegBankID:
+      // TODO: Check wavesize
+      return &AMDGPU::SReg_64_XEXECRegClass;
+    case AMDGPU::SGPRRegBankID:
+      return &AMDGPU::SReg_32_XM0RegClass;
+    case AMDGPU::SCCRegBankID:
+      // This needs to return an allocatable class, so don't bother returning
+      // the dummy SCC class.
+      return nullptr;
+    default:
+      llvm_unreachable("unknown register bank");
+    }
+  }
   case 32:
     return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
                                                   &AMDGPU::SReg_32_XM0RegClass;
   case 64:
     return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass :
                                                    &AMDGPU::SReg_64_XEXECRegClass;
   case 96:
     return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_96RegClass :

test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs  -global-isel-abort=0  -o - %s | FileCheck -check-prefixes=GCN %s
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs  -global-isel-abort=2 -pass-remarks-missed='gisel*'  -o /dev/null  %s 2>&1 | FileCheck -check-prefixes=ERR %s
 
+# G_IMPLICIT_DEF should probably never be produced for scc. Make sure there's no crash.
+# ERR: remark: <unknown>:0:0: cannot select: %0:scc(s1) = G_IMPLICIT_DEF (in function: implicit_def_s1_scc)
+# ERR-NOT: remark
+
+---
+
+name:            implicit_def_s32_sgpr
+legalized:       true
+regBankSelected: true
+
+body: |
+  bb.0:
+    ; GCN-LABEL: name: implicit_def_s32_sgpr
+    ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
+    ; GCN: S_ENDPGM 0, implicit [[DEF]]
+    %0:sgpr(s32) = G_IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...
 ---
 
-name:            implicit_def_s32
+name:            implicit_def_s32_vgpr
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
-    liveins: $vgpr3_vgpr4
-    ; GCN-LABEL: name: implicit_def_s32
-    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
+    ; GCN-LABEL: name: implicit_def_s32_vgpr
     ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GCN: FLAT_STORE_DWORD [[COPY]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
-    %0:vgpr(p1) = COPY $vgpr3_vgpr4
-    %1:vgpr(s32) = G_IMPLICIT_DEF
-    G_STORE %1, %0 :: (store 4, addrspace 1)
+    ; GCN: S_ENDPGM 0, implicit [[DEF]]
+    %0:vgpr(s32) = G_IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
 ...
+
 ---
 
-name:            implicit_def_s64
+name:            implicit_def_s64_sgpr
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
-    liveins: $vgpr3_vgpr4
-    ; GCN-LABEL: name: implicit_def_s64
-    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
-    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
-    ; GCN: FLAT_STORE_DWORDX2 [[COPY]], [[DEF]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
-    %0:vgpr(p1) = COPY $vgpr3_vgpr4
-    %1:vgpr(s64) = G_IMPLICIT_DEF
-    G_STORE %1, %0 :: (store 8, addrspace 1)
+    ; GCN-LABEL: name: implicit_def_s64_sgpr
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+    ; GCN: S_ENDPGM 0, implicit [[DEF]]
+    %0:sgpr(s64) = G_IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...
+
 ---
 
+name:            implicit_def_s64_vgpr
+legalized:       true
+regBankSelected: true
+
+body: |
+  bb.0:
+    ; GCN-LABEL: name: implicit_def_s64_vgpr
+    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; GCN: S_ENDPGM 0, implicit [[DEF]]
+    %0:vgpr(s64) = G_IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...
+
 ---
+name:            implicit_def_p0_sgpr
+legalized:       true
+regBankSelected: true
 
-name:            implicit_def_p0
+body: |
+  bb.0:
+    ; GCN-LABEL: name: implicit_def_p0_sgpr
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+    ; GCN: S_ENDPGM 0, implicit [[DEF]]
+    %0:sgpr(p0) = G_IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...
+
+---
+name:            implicit_def_p0_vgpr
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
+    ; GCN-LABEL: name: implicit_def_p0_vgpr
+    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+    ; GCN: S_ENDPGM 0, implicit [[DEF]]
     %0:vgpr(p0) = G_IMPLICIT_DEF
-    %1:vgpr(s32) = G_CONSTANT i32 4
-    G_STORE %1, %0 :: (store 4)
+    S_ENDPGM 0, implicit %0
 ...
 
 ---
 
-name:            implicit_def_p1
+name:            implicit_def_p1_vgpr
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
-    ; GCN-LABEL: name: implicit_def_p1
+    ; GCN-LABEL: name: implicit_def_p1_vgpr
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p1) = G_IMPLICIT_DEF
     %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
+
 ---
 
-name:            implicit_def_p3
+name:            implicit_def_p3_vgpr
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
-    ; GCN-LABEL: name: implicit_def_p3
+    ; GCN-LABEL: name: implicit_def_p3_vgpr
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p3) = G_IMPLICIT_DEF
     %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
+
 ---
 
-name:            implicit_def_p4
+name:            implicit_def_p4_vgpr
 legalized:       true
 regBankSelected: true
 
 body: |
   bb.0:
-    ; GCN-LABEL: name: implicit_def_p4
+    ; GCN-LABEL: name: implicit_def_p4_vgpr
     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p4) = G_IMPLICIT_DEF
     %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
+
+---
+
+name:            implicit_def_s1_vgpr
+legalized:       true
+regBankSelected: true
+
+body: |
+  bb.0:
+    ; GCN-LABEL: name: implicit_def_s1_vgpr
+    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN: S_ENDPGM 0, implicit [[DEF]]
+    %0:vgpr(s1) = G_IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...
+
+---
+
+name:            implicit_def_s1_sgpr
+legalized:       true
+regBankSelected: true
+
+body: |
+  bb.0:
+    ; GCN-LABEL: name: implicit_def_s1_sgpr
+    ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
+    ; GCN: S_ENDPGM 0, implicit [[DEF]]
+    %0:sgpr(s1) = G_IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...
+
+---
+
+name:            implicit_def_s1_scc
+legalized:       true
+regBankSelected: true
+
+body: |
+  bb.0:
+    ; GCN-LABEL: name: implicit_def_s1_scc
+    ; GCN: [[DEF:%[0-9]+]]:scc(s1) = G_IMPLICIT_DEF
+    ; GCN: S_ENDPGM 0, implicit [[DEF]](s1)
+    %0:scc(s1) = G_IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...
+
+---
+
+name:            implicit_def_s1_vcc
+legalized:       true
+regBankSelected: true
+
+body: |
+  bb.0:
+    ; GCN-LABEL: name: implicit_def_s1_vcc
+    ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+    ; GCN: S_ENDPGM 0, implicit [[DEF]]
+    %0:vcc(s1) = G_IMPLICIT_DEF
+    S_ENDPGM 0, implicit %0
+...