[Codegen] TargetLowering::SimplifySetCC(): omit urem when possible

[lebedev.ri]

Summary

This addresses the regression that is being exposed by D50222 in test/CodeGen/X86/jump_sign.ll
The missing fold, at least partially, looks trivial:
https://rise4fun.com/Alive/Zsln
i.e. if we are comparing with zero, and comparing the urem-by-non-power-of-two,
and the urem is of something that may at most have a single bit set (or no bits set at all),
the urem is not needed.

[xbolva00]

Thanks, you fixed it!

Can you add some new explicit tests for this fold?

[lebedev.ri]

+Standalone test coverage

[xbolva00]

Looks fine.

Thanks for alive proof as well!

[spatel]

LGTM. I have no idea if it's worth the trade-off, but we could do this sooner in IR (instcombine) instead of or in addition to SDAG?

[lebedev.ri]

Thank you for the reviews.

In D63390#1546676, @spatel wrote:

LGTM. I have no idea if it's worth the trade-off, but we could do this sooner in IR (instcombine) instead of or in addition to SDAG?

Indeed, this fold is missed in middle-end too, but the regression at hand is in back-end test,
so i'm not sure if we should just hand-wave and only fix it in middle-end.
Also, where should the middle-end fix be? Again InstCombine?

I'm also not sure if this is the best approach, the fold doesn't care *where* those bits are,
it only cares about the *count* of ones, and is thus easily defeated by shift operations,
as it is seen from tests.

[spatel]

In D63390#1546687, @lebedev.ri wrote:

Thank you for the reviews.

In D63390#1546676, @spatel wrote:

LGTM. I have no idea if it's worth the trade-off, but we could do this sooner in IR (instcombine) instead of or in addition to SDAG?

Indeed, this fold is missed in middle-end too, but the regression at hand is in back-end test,
so i'm not sure if we should just hand-wave and only fix it in middle-end.
Also, where should the middle-end fix be? Again InstCombine?

Yep, yet another clause under InstCombiner::visitICmpInst().

I'm also not sure if this is the best approach, the fold doesn't care *where* those bits are,
it only cares about the *count* of ones, and is thus easily defeated by shift operations,
as it is seen from tests.

True, although without some real-world evidence that this matters, I'd say "good enough". :)

[lebedev.ri]

:]

lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (N0.getOpcode() == ISD::ZERO_EXTEND) {
         if (Op0.getOpcode() == ISD::AssertZext &&
             cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
           return DAG.getSetCC(dl, VT, Op0,
                               DAG.getConstant(0, dl, Op0.getValueType()),
                               Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
       }
     }
 
+    // Given:
+    //   icmp eq/ne (urem %x, C), 0
+    // Iff C is not a power of two (those should not get to here though),
+    // and %x may have at most one bit set, omit the 'urem':
+    //   icmp eq/ne %x, 0
+    if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() &&
+        (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
+      if (auto *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1).getNode())) {
+        // We shouldn't have 'urem %x, power-of-2' by now, but just to be sure.
+        if (!N01C->getAPIntValue().isPowerOf2()) {
+          KnownBits Known = DAG.computeKnownBits(N0.getOperand(0));
+          if (Known.countMaxPopulation() == 1)
+            return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond);
+        }
+      }
+    }
+
     if (SDValue V =
             optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl))
       return V;
   }
 
   // These simplifications apply to splat vectors as well.
   // TODO: Handle more splat vector cases.
   if (auto *N1C = isConstOrConstSplat(N1)) {

test/CodeGen/X86/jump_sign.ll

 
 ; PR13966
 @b = common global i32 0, align 4
 @a = common global i32 0, align 4
 define i32 @func_test1(i32 %p1) nounwind uwtable {
 ; CHECK-LABEL: func_test1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl b, %eax
-; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    setb %cl
 ; CHECK-NEXT:    movl a, %eax
-; CHECK-NEXT:    andl %eax, %ecx
-; CHECK-NEXT:    imull $-85, %ecx, %ecx
-; CHECK-NEXT:    cmpb $86, %cl
-; CHECK-NEXT:    jb .LBB18_2
+; CHECK-NEXT:    testb %al, %cl
+; CHECK-NEXT:    je .LBB18_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    decl %eax
 ; CHECK-NEXT:    movl %eax, a
 ; CHECK-NEXT:  .LBB18_2: # %if.end
 ; CHECK-NEXT:    retl
 entry:
   %t0 = load i32, i32* @b, align 4
   %cmp = icmp ult i32 %t0, %p1