This is cpp source part of wave32 support, excluding overriden
getRegClass().
This is another split from D63204 to reduce it.
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| Differential D63351
[AMDGPU] gfx10 conditional registers handling ClosedPublic Authored by rampitec on Jun 14 2019, 11:57 AM.
Details Summary This is cpp source part of wave32 support, excluding overriden This is another split from D63204 to reduce it.
Diff Detail
Event TimelineHerald added subscribers: jsji, t-tye, tpr and 5 others. · View Herald TranscriptJun 14 2019, 11:57 AM This revision is now accepted and ready to land.Jun 16 2019, 10:05 AM Closed by commit rL363513: [AMDGPU] gfx10 conditional registers handling (authored by rampitec). · Explain WhyJun 16 2019, 10:09 AM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 204957 llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp
llvm/trunk/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp
llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp
llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp
llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/trunk/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
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