[TableGen] Add "getOperandType" to get operand types from opcode/opidx

[nlguillemot]

Summary

The InstrInfoEmitter outputs an enum called "OperandType" which gives numerical IDs to each operand type. This patch makes use of this enum to define a function called "getOperandType", which allows looking up the type of an operand given its opcode and operand index.

[nlguillemot]

• Fix some syntax mistakes.
• Map only records that derive from Operand and are not anonymous. This exactly matches the condition used to generate GET_INSTRINFO_OPERAND_TYPES_ENUM.

[nlguillemot]

some syntax nits:
OpcodeOperandTypes [] -> OpcodeOperandTypes[] (removed unnecessary space)
OS << "-1"; -> OS << -1; (don't use string where not necessary

[craig.topper]

Can the enum be used without this? I'm trying to understand why the enum was there to begin with. Only one in tree target, AVR, defines GET_INSTRINFO_OPERAND_TYPES_ENUM. Its not built by default so I could't really check, but looking through the file that included it, I couldn't prove it was being used.

[nlguillemot]

In D63320#1549309, @craig.topper wrote:

Can the enum be used without this? I'm trying to understand why the enum was there to begin with. Only one in tree target, AVR, defines GET_INSTRINFO_OPERAND_TYPES_ENUM. Its not built by default so I could't really check, but looking through the file that included it, I couldn't prove it was being used.

Indeed, I had the same question myself...

I couldn't find a particular way to use the enum otherwise myself, but I'm not an expert of the relevant code. MCOperandInfo does have a member that is somewhat misleadingly named OperandType, but that one seems to refer to llvm::MCOI::OperandType rather than this enum.

[nlguillemot]

ping

[dsanders]

LGTM

In D63320#1549309, @craig.topper wrote:

Can the enum be used without this? I'm trying to understand why the enum was there to begin with. Only one in tree target, AVR, defines GET_INSTRINFO_OPERAND_TYPES_ENUM. Its not built by default so I could't really check, but looking through the file that included it, I couldn't prove it was being used.

Enabling AVR and deleting the generated enum doesn't break anything so I don't think it's been used in-tree. I'm aware of two out-of-tree users (one of them being Nicolas :-)) and presumably AVR has one too as I'd be surprised if they added it without something that needed it given that nobody else has it.

One potential in-tree use I see for OpTypes is using it in TargetInstrInfo::verifyInstruction() to verify operand constraints without having to test the actual instruction. I suppose GISel Combiners could potentially use it to combine instructions while still honouring things like addressing-mode constraints.

utils/TableGen/InstrInfoEmitter.cpp

356–357 ↗

(On Diff #205433)

Given that you depend on GET_INSTRINFO_OPERAND_TYPES_ENUM, it may be worth moving this before GET_INSTRINFO_OPERAND_TYPES_ENUM and #define-ing it in this block. It doesn't matter too much though as it's easy enough to have the including source define them both

372 ↗

(On Diff #205433)

It would be nice if we could still see the multi-operand operand before expansion but we don't have a need for it so it's fine to leave it out for now

397 ↗

(On Diff #205433)

Does it make sense to factor out instructions with the same list to compress the table? I expect the number of rows would drop quite a bit as ISA's generally have a lot of commonality between and/or/xor/etc. and similar.

404 ↗

(On Diff #205433)

Whitespace nit after the //

[nlguillemot]

Could somebody do the commit for me? I don’t have commit access yet.

llvm/trunk/test/TableGen/get-operand-type.td

+// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+
+// Check that getOperandType has the expected info in it
+
+include "llvm/Target/Target.td"
+
+def archInstrInfo : InstrInfo { }
+
+def arch : Target {
+  let InstructionSet = archInstrInfo;
+}
+
+def Reg : Register<"reg">;
+def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
+
+def OpA : Operand<i32>;
+def OpB : Operand<i32>;
+
+def InstA : Instruction {
+  let Size = 1;
+  let OutOperandList = (outs OpA:$a);
+  let InOperandList = (ins OpB:$b, i32imm:$c);
+  field bits<8> Inst;
+  field bits<8> SoftFail = 0;
+  let Namespace = "MyNamespace";
+}
+
+def InstB : Instruction {
+  let Size = 1;
+  let OutOperandList = (outs i32imm:$d);
+  let InOperandList = (ins unknown:$x);
+  field bits<8> Inst;
+  field bits<8> SoftFail = 0;
+  let Namespace = "MyNamespace";
+}
+
+// CHECK: #ifdef GET_INSTRINFO_OPERAND_TYPE
+// CHECK: { OpTypes::OpA, OpTypes::OpB, OpTypes::i32imm, }
+// CHECK-NEXT: { OpTypes::i32imm, -1, }
+// CHECK: #endif //GET_INSTRINFO_OPERAND_TYPE

llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp

private:
   /// Expand TIIPredicate definitions to functions that accept a const MCInst
   /// reference.
   void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
   void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                   Record *InstrInfo,
                   std::map<std::vector<Record*>, unsigned> &EL,
                   const OperandInfoMapTy &OpInfo,
                   raw_ostream &OS);
-  void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target);
+  void emitOperandTypeMappings(
+      raw_ostream &OS, const CodeGenTarget &Target,
+      ArrayRef<const CodeGenInstruction *> NumberedInstructions);
   void initOperandMapData(
             ArrayRef<const CodeGenInstruction *> NumberedInstructions,
             StringRef Namespace,
             std::map<std::string, unsigned> &Operands,
             OpNameMapTy &OperandMap);
   void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
             ArrayRef<const CodeGenInstruction*> NumberedInstructions);
 
void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
   OS << "} // end namespace " << Namespace << "\n";
   OS << "} // end namespace llvm\n";
   OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n";
 }
 
 /// Generate an enum for all the operand types for this target, under the
 /// llvm::TargetNamespace::OpTypes namespace.
 /// Operand types are all definitions derived of the Operand Target.td class.
-void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS,
-                                            const CodeGenTarget &Target) {
+void InstrInfoEmitter::emitOperandTypeMappings(
+    raw_ostream &OS, const CodeGenTarget &Target,
+    ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
 
   StringRef Namespace = Target.getInstNamespace();
   std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
 
   OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
   OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
   OS << "namespace llvm {\n";
   OS << "namespace " << Namespace << " {\n";
   OS << "namespace OpTypes {\n";
   OS << "enum OperandType {\n";
 
   unsigned EnumVal = 0;
   for (const Record *Op : Operands) {
     if (!Op->isAnonymous())
       OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
     ++EnumVal;
   }
 
   OS << "  OPERAND_TYPE_LIST_END" << "\n};\n";
   OS << "} // end namespace OpTypes\n";
   OS << "} // end namespace " << Namespace << "\n";
   OS << "} // end namespace llvm\n";
   OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
+
+  OS << "#ifdef GET_INSTRINFO_OPERAND_TYPE\n";
+  OS << "#undef GET_INSTRINFO_OPERAND_TYPE\n";
+  OS << "namespace llvm {\n";
+  OS << "namespace " << Namespace << " {\n";
+  OS << "LLVM_READONLY\n";
+  OS << "int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
+  if (!NumberedInstructions.empty()) {
+    OS << "  static const std::initializer_list<int> OpcodeOperandTypes[] = "
+          "{\n";
+    for (const CodeGenInstruction *Inst : NumberedInstructions) {
+      OS << "    { ";
+      for (const auto &Op : Inst->Operands) {
+        // Handle aggregate operands and normal operands the same way by
+        // expanding either case into a list of operands for this op.
+        std::vector<CGIOperandList::OperandInfo> OperandList;
+
+        const DagInit *MIOI = Op.MIOperandInfo;
+        if (!MIOI || MIOI->getNumArgs() == 0) {
+          // Single, anonymous, operand.
+          OperandList.push_back(Op);
+        } else {
+          for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
+            OperandList.push_back(Op);
+
+            auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
+            OperandList.back().Rec = OpR;
+          }
+        }
+
+        for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
+          Record *OpR = OperandList[j].Rec;
+          if (OpR->isSubClassOf("Operand") && !OpR->isAnonymous())
+            OS << "OpTypes::" << OpR->getName();
+          else
+            OS << -1;
+          OS << ", ";
+        }
+      }
+      OS << "},\n";
+    }
+    OS << "  };\n";
+    OS << "  return OpcodeOperandTypes[Opcode].begin()[OpIdx];\n";
+  } else {
+    OS << "  llvm_unreachable(\"No instructions defined\");\n";
+  }
+  OS << "}\n";
+  OS << "} // end namespace " << Namespace << "\n";
+  OS << "} // end namespace llvm\n";
+  OS << "#endif //GET_INSTRINFO_OPERAND_TYPE\n\n";
 }
 
 void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
                                              StringRef TargetName) {
   RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
   if (TIIPredicates.empty())
     return;
 
OS << ClassName << "::" << ClassName
      << "InstrNameIndices, " << TargetName << "InstrNameData, "
      << NumberedInstructions.size() << ");\n}\n";
   OS << "} // end llvm namespace\n";
 
   OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
 
   emitOperandNameMappings(OS, Target, NumberedInstructions);
 
-  emitOperandTypesEnum(OS, Target);
+  emitOperandTypeMappings(OS, Target, NumberedInstructions);
 
   emitMCIIHelperMethods(OS, TargetName);
 }
 
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   Record *InstrInfo,
                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
                                   const OperandInfoMapTy &OpInfo,