AMDGPU: Fold readlane intrinsics of constants

[arsenm]

Summary

I'm not 100% sure about this, since I'm worried about IR transforms
that might end up introducing divergence downstream once replaced with
a constant, but I haven't come up with an example yet.

[rampitec]

How this can even happen? Someone needs to use an intrinsic on a literal? This use doesn't make a lot of sense. Do you have a real example of such use?

[arsenm]

In D63226#1540466, @rampitec wrote:

How this can even happen? Someone needs to use an intrinsic on a literal? This use doesn't make a lot of sense. Do you have a real example of such use?

You can use readfirstlane to effectively assert that a function argument must be uniform. After inlining, it might see a constant

[rampitec]

LGTM

[arsenm]

r363406

lib/Transforms/InstCombine/InstCombineCalls.cpp

if (BC->isZeroValue() ||
         BM->getZExtValue() != 0xF ||
         isa<UndefValue>(Old))
       break;
 
     // If bound_ctrl = 1, row mask = bank mask = 0xf we can omit old value.
     II->setOperand(0, UndefValue::get(Old->getType()));
     return II;
   }
+  case Intrinsic::amdgcn_readfirstlane:
+  case Intrinsic::amdgcn_readlane: {
+    // A constant value is trivially uniform.
+    if (Constant *C = dyn_cast<Constant>(II->getArgOperand(0)))
+      return replaceInstUsesWith(*II, C);
+    break;
+  }
   case Intrinsic::stackrestore: {
     // If the save is right next to the restore, remove the restore.  This can
     // happen when variable allocas are DCE'd.
     if (IntrinsicInst *SS = dyn_cast<IntrinsicInst>(II->getArgOperand(0))) {
       if (SS->getIntrinsicID() == Intrinsic::stacksave) {
         // Skip over debug info.
         if (SS->getNextNonDebugInstruction() == II) {
           return eraseInstFromFunction(CI);

test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll

 ; CHECK-LABEL: @kill_true(
 ; CHECK-NEXT:    ret void
 ;
   call void @llvm.amdgcn.kill(i1 true)
   ret void
 }
 
 ; --------------------------------------------------------------------
+; llvm.amdgcn.readfirstlane
+; --------------------------------------------------------------------
+
+declare i32 @llvm.amdgcn.readfirstlane(i32)
+
+@gv = constant i32 0
+
+define amdgpu_kernel void @readfirstlane_constant(i32 %arg) {
+; CHECK-LABEL: @readfirstlane_constant(
+; CHECK-NEXT: %var = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)
+; CHECK-NEXT: store volatile i32 %var, i32* undef, align 4
+; CHECK-NEXT: store volatile i32 0, i32* undef, align 4
+; CHECK-NEXT: store volatile i32 123, i32* undef, align 4
+; CHECK-NEXT: store volatile i32 ptrtoint (i32* @gv to i32), i32* undef, align 4
+; CHECK-NEXT: store volatile i32 undef, i32* undef, align 4
+  %var = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)
+  %zero = call i32 @llvm.amdgcn.readfirstlane(i32 0)
+  %imm = call i32 @llvm.amdgcn.readfirstlane(i32 123)
+  %constexpr = call i32 @llvm.amdgcn.readfirstlane(i32 ptrtoint (i32* @gv to i32))
+  %undef = call i32 @llvm.amdgcn.readfirstlane(i32 undef)
+  store volatile i32 %var, i32* undef
+  store volatile i32 %zero, i32* undef
+  store volatile i32 %imm, i32* undef
+  store volatile i32 %constexpr, i32* undef
+  store volatile i32 %undef, i32* undef
+  ret void
+}
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.readlane
+; --------------------------------------------------------------------
+
+declare i32 @llvm.amdgcn.readlane(i32, i32)
+
+define amdgpu_kernel void @readlane_constant(i32 %arg, i32 %lane) {
+; CHECK-LABEL: @readlane_constant(
+; CHECK-NEXT: %var = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 7)
+; CHECK-NEXT: store volatile i32 %var, i32* undef, align 4
+; CHECK-NEXT: store volatile i32 0, i32* undef, align 4
+; CHECK-NEXT: store volatile i32 123, i32* undef, align 4
+; CHECK-NEXT: store volatile i32 ptrtoint (i32* @gv to i32), i32* undef, align 4
+; CHECK-NEXT: store volatile i32 undef, i32* undef, align 4
+  %var = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 7)
+  %zero = call i32 @llvm.amdgcn.readlane(i32 0, i32 %lane)
+  %imm = call i32 @llvm.amdgcn.readlane(i32 123, i32 %lane)
+  %constexpr = call i32 @llvm.amdgcn.readlane(i32 ptrtoint (i32* @gv to i32), i32 %lane)
+  %undef = call i32 @llvm.amdgcn.readlane(i32 undef, i32 %lane)
+  store volatile i32 %var, i32* undef
+  store volatile i32 %zero, i32* undef
+  store volatile i32 %imm, i32* undef
+  store volatile i32 %constexpr, i32* undef
+  store volatile i32 %undef, i32* undef
+  ret void
+}
+
+; --------------------------------------------------------------------
 ; llvm.amdgcn.update.dpp.i32
 ; --------------------------------------------------------------------
 
 declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)
 
 define amdgpu_kernel void @update_dpp_no_combine(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
 ; CHECK-LABEL: @update_dpp_no_combine(
 ; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 [[IN1:%.*]], i32 [[IN2:%.*]], i32 1, i32 1, i32 1, i1 false)