[InstCombine] Fold icmp eq/ne (and %x, signbit), 0 -> %x s>=/s< 0 earlier

[huihuiz]

Summary

To generate simplified IR, make sure fold

(X & signbit) ==/!= 0) -> X s>=/s< 0;

is scheduled before fold

((X << Y) & C) == 0 -> (X & (C >> Y)) == 0.

https://rise4fun.com/Alive/fbdh

[huihuiz]

This fix D63025
Split from D62818

[lebedev.ri]

Yep, first fold looks good, some nits.

lib/Transforms/InstCombine/InstCombineCompares.cpp

1643–1644

Move after the newly added code, this restriction does not apply for the pattern in question.

1654

X u< 8

1654–1662

I'm sorry that i keep nagging, but this is a second, not unrelated, but separate fold.
Please put it into a separate review :)

test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll

125 ↗

(On Diff #204435)

It didn't though (:

142 ↗

(On Diff #204435)

Similarly, should fold.

160 ↗

(On Diff #204435)

Here too

[huihuiz]

lib/Transforms/InstCombine/InstCombineCompares.cpp

1643–1644

The restriction "And operation having only one use" was introduced in r134379 (resolving PR10267).

When And operation has more than one use, applying the following folds will transform an equality compare into an inequality compare, without cutting done any extra instructions. Inequalities are generally more expensive.

This restriction should apply to fold "(X & signbit) ==/!= 0) --> X s>=/s< 0"and "((X & ~C) ==/!= 0) C+1 is power of 2 --> X u</u>= C+1".

test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll

125 ↗

(On Diff #204435)

Actually fold happened even without this reordering.
look for the generate ll

**%shl = shl i32 %x, %y**
%xor = xor i32 %shl, %z
store i32 %xor, i32* %p, align 4
**%r = icmp sgt i32 %shl, -1**

we are trying to schedule (X & signbit) ==/!= 0) -> X s>=/s< 0; before ((X << Y) & C) == 0 -> (X & (C >> Y)) == 0.
The second fold has restriction on "shift having only one use", which failed for this case.

So fold happened even without reorder, extra use of shift doesn't restrict on the first fold

142 ↗

(On Diff #204435)

Should still comply with restriction on "And operation having only one use", as explained in r134379.

160 ↗

(On Diff #204435)

Similar as above. And operation has extra use, should comply with the restriction.

[lebedev.ri]

lib/Transforms/InstCombine/InstCombineCompares.cpp

1643–1644

Aha, thank you for digging that up.

The restriction "And operation having only one use" was introduced in r134379 (resolving PR10267).
When And operation has more than one use, applying the following folds will transform an equality compare into an inequality compare, without cutting done any extra instructions. Inequalities are generally more expensive.

All that (including rL134379) reads wrong to me.
There is no such cost-model in middle-end,
here in instcombine we only care about not increasing instruction count.
If something is worse for backend/target, then the opposite fold should be done in backend.

Not having this one-use restriction does not result in increasing
instruction count, and decreases "the dependency chain" of the icmp,
since it no longer depends on and, i.e. the restriction is incorrect/harmful.

But i suppose lifting it up first requires a backend fix, so let's leave it for now :/

[lebedev.ri]

I think this looks good now, thank you for working on this!
Can you please link the patch into which you split the second fold from here?

lib/Transforms/InstCombine/InstCombineCompares.cpp

1025–1033

Can you please link the patch to which you split this out?

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

1647 ↗

(On Diff #205388)

Please add a comment about the reason (PR10267) this fold is restricted to one-use and.

[lebedev.ri]

Hmm, here too, an undo fold seems to be missing https://godbolt.org/z/T9NwwJ

[huihuiz]

this differential update address inline comment - adding comment for restriction this fold to single-use 'and' (PR10267)

lib/Transforms/InstCombine/InstCombineCompares.cpp

   // can therefore act as if any such guesses are wrong.
   //
   // The code below checks that the alloca doesn't escape, and that it's only
   // used in a comparison once (the current instruction). The
   // single-comparison-use condition ensures that we're trivially folding all
   // comparisons against the alloca consistently, and avoids the risk of
   // erroneously folding a comparison of the pointer with itself.
 
   unsigned MaxIter = 32; // Break cycles and bound to constant-time.
 
   SmallVector<const Use *, 32> Worklist;
   for (const Use &U : Alloca->uses()) {
     if (Worklist.size() >= MaxIter)
       return nullptr;
     Worklist.push_back(&U);
   }
 
   unsigned NumCmps = 0;
   while (!Worklist.empty()) {
     assert(Worklist.size() <= MaxIter);
     const Use *U = Worklist.pop_back_val();
     const Value *V = U->getUser();
     --MaxIter;
 
     if (isa<BitCastInst>(V) || isa<GetElementPtrInst>(V) || isa<PHINode>(V) ||

 
   return nullptr;
 }
 
 /// Fold icmp (and X, C2), C1.
 Instruction *InstCombiner::foldICmpAndConstConst(ICmpInst &Cmp,
                                                  BinaryOperator *And,
                                                  const APInt &C1) {
+  bool isICMP_NE = Cmp.getPredicate() == ICmpInst::ICMP_NE;
+
   // For vectors: icmp ne (and X, 1), 0 --> trunc X to N x i1
   // TODO: We canonicalize to the longer form for scalars because we have
   // better analysis/folds for icmp, and codegen may be better with icmp.
-  if (Cmp.getPredicate() == CmpInst::ICMP_NE && Cmp.getType()->isVectorTy() &&
-      C1.isNullValue() && match(And->getOperand(1), m_One()))
+  if (isICMP_NE && Cmp.getType()->isVectorTy() && C1.isNullValue() &&
+      match(And->getOperand(1), m_One()))
     return new TruncInst(And->getOperand(0), Cmp.getType());
 
   const APInt *C2;
-  if (!match(And->getOperand(1), m_APInt(C2)))
+  Value *X;
+  if (!match(And, m_And(m_Value(X), m_APInt(C2))))
     return nullptr;
 
   if (!And->hasOneUse())
     return nullptr;
 
+  if (Cmp.isEquality() && C1.isNullValue()) {
+    // Replace (and X, (1 << size(X)-1) != 0) with X s< 0
+    if (C2->isSignMask()) {
+      Constant *Zero = Constant::getNullValue(X->getType());
+      auto NewPred = isICMP_NE ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_SGE;
+      return new ICmpInst(NewPred, X, Zero);
+    }
+
+    // ((X & ~7) == 0) --> X < 8
+    // If X is (BinOp Y, C3), allow other rules to fold C3 with C2.
+    if (!match(X, m_c_BinOp(m_Value(), m_Constant())) &&
+        (~(*C2) + 1).isPowerOf2()) {
+      Constant *NegBOC =
+          ConstantExpr::getNeg(cast<Constant>(And->getOperand(1)));
+      auto NewPred = isICMP_NE ? ICmpInst::ICMP_UGE : ICmpInst::ICMP_ULT;
+      return new ICmpInst(NewPred, X, NegBOC);
+    }
+  }
+
   // If the LHS is an 'and' of a truncate and we can widen the and/compare to
   // the input width without changing the value produced, eliminate the cast:
   //
   // icmp (and (trunc W), C2), C1 -> icmp (and W, C2'), C1'
   //
   // We can do this transformation if the constants do not have their sign bits
   // set or if it is an equality comparison. Extending a relational comparison
   // when we're checking the sign bit would not work.

   }
   case Instruction::And: {
     const APInt *BOC;
     if (match(BOp1, m_APInt(BOC))) {
       // If we have ((X & C) == C), turn it into ((X & C) != 0).
       if (C == *BOC && C.isPowerOf2())
         return new ICmpInst(isICMP_NE ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE,
                             BO, Constant::getNullValue(RHS->getType()));
-
-      // Don't perform the following transforms if the AND has multiple uses
-      if (!BO->hasOneUse())
-        break;
-
-      // Replace (and X, (1 << size(X)-1) != 0) with x s< 0
-      if (BOC->isSignMask()) {
-        Constant *Zero = Constant::getNullValue(BOp0->getType());
-        auto NewPred = isICMP_NE ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_SGE;
-        return new ICmpInst(NewPred, BOp0, Zero);
-      }
-
-      // ((X & ~7) == 0) --> X < 8
-      if (C.isNullValue() && (~(*BOC) + 1).isPowerOf2()) {
-        Constant *NegBOC = ConstantExpr::getNeg(cast<Constant>(BOp1));
-        auto NewPred = isICMP_NE ? ICmpInst::ICMP_UGE : ICmpInst::ICMP_ULT;
-        return new ICmpInst(NewPred, BOp0, NegBOC);
-      }
     }
     break;
   }
   case Instruction::Mul:
     if (C.isNullValue() && BO->hasNoSignedWrap()) {
       const APInt *BOC;
       if (match(BOp1, m_APInt(BOC)) && !BOC->isNullValue()) {
         // The trivial case (mul X, 0) is handled by InstSimplify.

test/Transforms/InstCombine/icmp-shift-and-negC.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -instcombine -S | FileCheck %s
 
 
-; FIXME: expect ((X << Y) & ~C) ==/!= 0 -> (X << Y) </>= C+1; C+1 is power of 2
+; Checking:
+; ((X << Y) & ~C) ==/!= 0 -> (X << Y) </>= C+1; C+1 is power of 2
+; ((X l>> Y) & ~C) ==/!= 0 -> (X l>> Y) </>= C+1; C+1 is power of 2
+
 define i1 @shl-and-negC(i32 %x, i32 %y) {
 ; CHECK-LABEL: @shl-and-negC(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 -8, [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ugt i32 [[SHL]], 7
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %shl = shl i32 %x, %y
   %and = and i32 %shl, 4294967288  ; ~7
   %r = icmp ne i32 %and, 0
   ret i1 %r
 }
 
-; FIXME: expect ((X l>> Y) & ~C) ==/!= 0 -> (X l>> Y) </>= C+1; C+1 is power of 2
 define i1 @lshr-and-negC(i32 %x, i32 %y) {
 ; CHECK-LABEL: @lshr-and-negC(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 -8, [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[TMP2]], 0
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ult i32 [[LSHR]], 8
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %lshr = lshr i32 %x, %y
   %and = and i32 %lshr, 4294967288  ; ~7
   %r = icmp eq i32 %and, 0
   ret i1 %r
 }
+
+define <2 x i1> @lshr-and-negC-vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @lshr-and-negC-vec(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ult <2 x i32> [[LSHR]], <i32 8, i32 8>
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %lshr = lshr <2 x i32> %x, %y
+  %and = and <2 x i32> %lshr, <i32 4294967288, i32 4294967288>  ; ~7
+  %r = icmp eq <2 x i32> %and, <i32 0, i32 0>
+  ret <2 x i1> %r
+}
+
+define <3 x i1> @lshr-and-negC-vec-undef1(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @lshr-and-negC-vec-undef1(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr <3 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[LSHR]], <i32 -8, i32 undef, i32 -8>
+; CHECK-NEXT:    [[R:%.*]] = icmp eq <3 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT:    ret <3 x i1> [[R]]
+;
+  %lshr = lshr <3 x i32> %x, %y
+  %and = and <3 x i32> %lshr, <i32 4294967288, i32 undef, i32 4294967288>  ; ~7
+  %r = icmp eq <3 x i32> %and, <i32 0, i32 0, i32 0>
+  ret <3 x i1> %r
+}
+
+define <3 x i1> @lshr-and-negC-vec-undef2(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @lshr-and-negC-vec-undef2(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr <3 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[LSHR]], <i32 -8, i32 -8, i32 -8>
+; CHECK-NEXT:    [[R:%.*]] = icmp eq <3 x i32> [[AND]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i1> [[R]]
+;
+  %lshr = lshr <3 x i32> %x, %y
+  %and = and <3 x i32> %lshr, <i32 4294967288, i32 4294967288, i32 4294967288>  ; ~7
+  %r = icmp eq <3 x i32> %and, <i32 0, i32 undef, i32 0>
+  ret <3 x i1> %r
+}
+
+define <3 x i1> @lshr-and-negC-vec-undef3(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @lshr-and-negC-vec-undef3(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr <3 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[LSHR]], <i32 -8, i32 undef, i32 -8>
+; CHECK-NEXT:    [[R:%.*]] = icmp eq <3 x i32> [[AND]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i1> [[R]]
+;
+  %lshr = lshr <3 x i32> %x, %y
+  %and = and <3 x i32> %lshr, <i32 4294967288, i32 undef, i32 4294967288>  ; ~7
+  %r = icmp eq <3 x i32> %and, <i32 0, i32 undef, i32 0>
+  ret <3 x i1> %r
+}
+
+define i1 @shl-and-negC-extra-use-shl(i32 %x, i32 %y, i32 %z, i32* %p) {
+; CHECK-LABEL: @shl-and-negC-extra-use-shl(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[XOR:%.*]] = xor i32 [[SHL]], [[Z:%.*]]
+; CHECK-NEXT:    store i32 [[XOR]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = icmp ugt i32 [[SHL]], 7
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 %x, %y
+  %xor = xor i32 %shl, %z  ; extra use of shl
+  store i32 %xor, i32* %p
+  %and = and i32 %shl, 4294967288  ; ~7
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}
+
+define i1 @shl-and-negC-extra-use-and(i32 %x, i32 %y, i32 %z, i32* %p) {
+; CHECK-LABEL: @shl-and-negC-extra-use-and(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], -8
+; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[AND]], [[Z:%.*]]
+; CHECK-NEXT:    store i32 [[MUL]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 %x, %y
+  %and = and i32 %shl, 4294967288  ; ~7
+  %mul = mul i32 %and, %z  ; extra use of and
+  store i32 %mul, i32* %p
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}
+
+define i1 @shl-and-negC-extra-use-shl-and(i32 %x, i32 %y, i32 %z, i32* %p) {
+; CHECK-LABEL: @shl-and-negC-extra-use-shl-and(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], -8
+; CHECK-NEXT:    [[XOR:%.*]] = xor i32 [[AND]], [[Z:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SHL]], [[XOR]]
+; CHECK-NEXT:    store i32 [[ADD]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 %x, %y
+  %and = and i32 %shl, 4294967288  ; ~7
+  %xor = xor i32 %and, %z  ; extra use of and
+  %add = add i32 %shl, %xor  ; extra use of shl
+  store i32 %add, i32* %p
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}

test/Transforms/InstCombine/icmp-shift-and-signbit.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -instcombine -S | FileCheck %s
 
-; FIXME: expect ((X << Y) & signbit) ==/!= 0 -> (X << Y) >=/< 0
+; Checking:
+; ((X << Y) & signbit) ==/!= 0 -> (X << Y) >=/< 0
+; ((X l>> Y) & signbit) ==/!= 0 -> (X l>> Y) >=/< 0
+
 define i1 @shl-and-signbit(i32 %x, i32 %y) {
 ; CHECK-LABEL: @shl-and-signbit(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 -2147483648, [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[TMP2]], 0
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[SHL]], 0
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %shl = shl i32 %x, %y
   %and = and i32 %shl, -2147483648
   %r = icmp ne i32 %and, 0
   ret i1 %r
 }
 
-; FIXME: expect ((X l>> Y) & signbit) ==/!= 0 -> (X l>> Y) >=/< 0
 define i1 @lshr-and-signbit(i32 %x, i32 %y) {
 ; CHECK-LABEL: @lshr-and-signbit(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 -2147483648, [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[TMP2]], 0
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[LSHR]], -1
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %lshr = lshr i32 %x, %y
   %and = and i32 %lshr, -2147483648
   %r = icmp eq i32 %and, 0
   ret i1 %r
 }
+
+define <2 x i1> @lshr-and-signbit-vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @lshr-and-signbit-vec(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp slt <2 x i32> [[LSHR]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %lshr = lshr <2 x i32> %x, %y
+  %and = and <2 x i32> %lshr, <i32 -2147483648, i32 -2147483648>
+  %r = icmp ne <2 x i32> %and, <i32 0, i32 0>
+  ret <2 x i1> %r
+}
+
+define <3 x i1> @lshr-and-signbit-vec-undef1(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @lshr-and-signbit-vec-undef1(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr <3 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[LSHR]], <i32 -2147483648, i32 undef, i32 -2147483648>
+; CHECK-NEXT:    [[R:%.*]] = icmp ne <3 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT:    ret <3 x i1> [[R]]
+;
+  %lshr = lshr <3 x i32> %x, %y
+  %and = and <3 x i32> %lshr, <i32 -2147483648, i32 undef, i32 -2147483648>
+  %r = icmp ne <3 x i32> %and, <i32 0, i32 0, i32 0>
+  ret <3 x i1> %r
+}
+
+define <3 x i1> @lshr-and-signbit-vec-undef2(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @lshr-and-signbit-vec-undef2(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr <3 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[LSHR]], <i32 -2147483648, i32 -2147483648, i32 -2147483648>
+; CHECK-NEXT:    [[R:%.*]] = icmp eq <3 x i32> [[AND]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i1> [[R]]
+;
+  %lshr = lshr <3 x i32> %x, %y
+  %and = and <3 x i32> %lshr, <i32 -2147483648, i32 -2147483648, i32 -2147483648>
+  %r = icmp eq <3 x i32> %and, <i32 0, i32 undef, i32 0>
+  ret <3 x i1> %r
+}
+
+define <3 x i1> @lshr-and-signbit-vec-undef3(<3 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @lshr-and-signbit-vec-undef3(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr <3 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and <3 x i32> [[LSHR]], <i32 -2147483648, i32 undef, i32 -2147483648>
+; CHECK-NEXT:    [[R:%.*]] = icmp ne <3 x i32> [[AND]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i1> [[R]]
+;
+  %lshr = lshr <3 x i32> %x, %y
+  %and = and <3 x i32> %lshr, <i32 -2147483648, i32 undef, i32 -2147483648>
+  %r = icmp ne <3 x i32> %and, <i32 0, i32 undef, i32 0>
+  ret <3 x i1> %r
+}
+
+define i1 @shl-and-signbit-extra-use-shl(i32 %x, i32 %y, i32 %z, i32* %p) {
+; CHECK-LABEL: @shl-and-signbit-extra-use-shl(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[XOR:%.*]] = xor i32 [[SHL]], [[Z:%.*]]
+; CHECK-NEXT:    store i32 [[XOR]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[SHL]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 %x, %y
+  %xor = xor i32 %shl, %z  ; extra use of shl
+  store i32 %xor, i32* %p
+  %and = and i32 %shl, -2147483648
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}
+
+define i1 @shl-and-signbit-extra-use-and(i32 %x, i32 %y, i32 %z, i32* %p) {
+; CHECK-LABEL: @shl-and-signbit-extra-use-and(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], -2147483648
+; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[AND]], [[Z:%.*]]
+; CHECK-NEXT:    store i32 [[MUL]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 %x, %y
+  %and = and i32 %shl, -2147483648
+  %mul = mul i32 %and, %z  ; extra use of and
+  store i32 %mul, i32* %p
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}
+
+define i1 @shl-and-signbit-extra-use-shl-and(i32 %x, i32 %y, i32 %z, i32* %p) {
+; CHECK-LABEL: @shl-and-signbit-extra-use-shl-and(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], -2147483648
+; CHECK-NEXT:    [[XOR:%.*]] = xor i32 [[AND]], [[Z:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SHL]], [[XOR]]
+; CHECK-NEXT:    store i32 [[ADD]], i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 %x, %y
+  %and = and i32 %shl, -2147483648
+  %xor = xor i32 %and, %z  ; extra use of and
+  %add = add i32 %shl, %xor  ; extra use of shl
+  store i32 %add, i32* %p
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}