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Differential D62903

[MIPS GlobalISel] Select fabs
ClosedPublic

Authored by Petar.Avramovic on Jun 5 2019, 7:37 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG0a1fd355b2f6: [MIPS GlobalISel] Select fabs
rL362690: [MIPS GlobalISel] Select fabs
Summary

Select G_FABS for MIPS32.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Jun 5 2019, 7:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 5 2019, 7:37 AM
Herald added subscribers: llvm-commits, jrtc27, arichardson and 3 others. · View Herald Transcript
atanasyan accepted this revision.Jun 5 2019, 1:12 PM

LGTM

This revision is now accepted and ready to land.Jun 5 2019, 1:12 PM
Closed by commit rL362690: [MIPS GlobalISel] Select fabs (authored by Petar.Avramovic). · Explain WhyJun 6 2019, 2:19 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
10 lines
2 lines
3 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
65 lines
legalizer/
61 lines
llvm-ir/
27 lines
regbankselect/
63 lines

Diff 203310

llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp

Show First 20 Lines • Show All 351 Lines • ▼ Show 20 Lines if (Size == 64) {
{I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh}); {I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh});
if (!PairF64.constrainAllUses(TII, TRI, RBI)) if (!PairF64.constrainAllUses(TII, TRI, RBI))
return false; return false;
} }
I.eraseFromParent(); I.eraseFromParent();
return true; return true;
} }
case G_FABS: {
unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
unsigned FABSOpcode =
Size == 32 ? Mips::FABS_S
: STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32;
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode))
.add(I.getOperand(0))
.add(I.getOperand(1));
break;
}
case G_GLOBAL_VALUE: { case G_GLOBAL_VALUE: {
const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal(); const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
if (MF.getTarget().isPositionIndependent()) { if (MF.getTarget().isPositionIndependent()) {
MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
.addDef(I.getOperand(0).getReg()) .addDef(I.getOperand(0).getReg())
.addReg(MF.getInfo<MipsFunctionInfo>() .addReg(MF.getInfo<MipsFunctionInfo>()
->getGlobalBaseRegForGlobalISel()) ->getGlobalBaseRegForGlobalISel())
.addGlobalAddress(GVal); .addGlobalAddress(GVal);
▲ Show 20 Lines • Show All 221 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder(G_GLOBAL_VALUE) getActionDefinitionsBuilder(G_GLOBAL_VALUE)
.legalFor({p0}); .legalFor({p0});
// FP instructions // FP instructions
getActionDefinitionsBuilder(G_FCONSTANT) getActionDefinitionsBuilder(G_FCONSTANT)
.legalFor({s32, s64}); .legalFor({s32, s64});
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS})
.legalFor({s32, s64}); .legalFor({s32, s64});
getActionDefinitionsBuilder(G_FCMP) getActionDefinitionsBuilder(G_FCMP)
.legalFor({{s32, s32}, {s32, s64}}) .legalFor({{s32, s32}, {s32, s64}})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR}) getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
.libcallFor({s32, s64}); .libcallFor({s32, s64});
Show All 22 Lines

llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 LinesMipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_UDIV: case G_UDIV:
case G_SREM: case G_SREM:
case G_UREM: case G_UREM:
OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
break; break;
case G_FADD: case G_FADD:
case G_FSUB: case G_FSUB:
case G_FMUL: case G_FMUL:
case G_FDIV: { case G_FDIV:
case G_FABS: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
assert((Size == 32 || Size == 64) && "Unsupported floating point size"); assert((Size == 32 || Size == 64) && "Unsupported floating point size");
OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx] OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
: &Mips::ValueMappings[Mips::DPRIdx]; : &Mips::ValueMappings[Mips::DPRIdx];
break; break;
} }
case G_FCONSTANT: { case G_FCONSTANT: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fabs_f32() {entry: ret void}
define void @fabs_f64() {entry: ret void}
...
---
name: fabs_f32
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: fabs_f32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[FABS_S:%[0-9]+]]:fgr32 = FABS_S [[COPY]]
; FP32: $f0 = COPY [[FABS_S]]
; FP32: RetRA implicit $f0
; FP64-LABEL: name: fabs_f32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[FABS_S:%[0-9]+]]:fgr32 = FABS_S [[COPY]]
; FP64: $f0 = COPY [[FABS_S]]
; FP64: RetRA implicit $f0
%0:fprb(s32) = COPY $f12
%1:fprb(s32) = G_FABS %0
$f0 = COPY %1(s32)
RetRA implicit $f0
...
---
name: fabs_f64
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: fabs_f64
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[FABS_D32_:%[0-9]+]]:afgr64 = FABS_D32 [[COPY]]
; FP32: $d0 = COPY [[FABS_D32_]]
; FP32: RetRA implicit $d0
; FP64-LABEL: name: fabs_f64
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[FABS_D64_:%[0-9]+]]:fgr64 = FABS_D64 [[COPY]]
; FP64: $d0 = COPY [[FABS_D64_]]
; FP64: RetRA implicit $d0
%0:fprb(s64) = COPY $d6
%1:fprb(s64) = G_FABS %0
$d0 = COPY %1(s64)
RetRA implicit $d0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fabs_f32() {entry: ret void}
define void @fabs_f64() {entry: ret void}
...
---
name: fabs_f32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: fabs_f32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
; FP32: $f0 = COPY [[FABS]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: fabs_f32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
; FP64: $f0 = COPY [[FABS]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = COPY $f12
%1:_(s32) = G_FABS %0
$f0 = COPY %1(s32)
RetRA implicit $f0
...
---
name: fabs_f64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: fabs_f64
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
; FP32: $d0 = COPY [[FABS]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: fabs_f64
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
; FP64: $d0 = COPY [[FABS]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = COPY $d6
%1:_(s64) = G_FABS %0
$d0 = COPY %1(s64)
RetRA implicit $d0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
declare float @llvm.fabs.f32(float)
define float @fabs_f32(float %a) {
; MIPS32-LABEL: fabs_f32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: abs.s $f0, $f12
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%0 = call float @llvm.fabs.f32(float %a)
ret float %0
}
declare double @llvm.fabs.f64(double)
define double @fabs_f64(double %a) {
; MIPS32-LABEL: fabs_f64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: abs.d $f0, $f12
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%0 = call double @llvm.fabs.f64(double %a)
ret double %0
}

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fabs_f32() {entry: ret void}
define void @fabs_f64() {entry: ret void}
...
---
name: fabs_f32
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: fabs_f32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP32: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]]
; FP32: $f0 = COPY [[FABS]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: fabs_f32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
; FP64: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]]
; FP64: $f0 = COPY [[FABS]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = COPY $f12
%1:_(s32) = G_FABS %0
$f0 = COPY %1(s32)
RetRA implicit $f0
...
---
name: fabs_f64
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: fabs_f64
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP32: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]]
; FP32: $d0 = COPY [[FABS]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: fabs_f64
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
; FP64: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]]
; FP64: $d0 = COPY [[FABS]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = COPY $d6
%1:_(s64) = G_FABS %0
$d0 = COPY %1(s64)
RetRA implicit $d0
...