This is an archive of the discontinued LLVM Phabricator instance.

Differential D62901

[MIPS GlobalISel] Select floor and ceil
ClosedPublic

Authored by Petar.Avramovic on Jun 5 2019, 7:35 AM.

Details

Reviewers
atanasyan
petarj
Commits
rGfaaa2b5d2156: [MIPS GlobalISel] Select floor and ceil
rL362688: [MIPS GlobalISel] Select floor and ceil
Summary

Select G_FFLOOR and G_FCEIL for MIPS32.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Jun 5 2019, 7:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 5 2019, 7:35 AM
Herald added subscribers: llvm-commits, volkan, jrtc27 and 4 others. · View Herald Transcript
atanasyan accepted this revision.Jun 5 2019, 1:08 PM

LGTM with a nit.

lib/CodeGen/GlobalISel/LegalizerHelper.cpp
279 ↗(On Diff #203145)

Add space before colon.

282 ↗(On Diff #203145)

Ditto.

This revision is now accepted and ready to land.Jun 5 2019, 1:08 PM
Closed by commit rL362688: [MIPS GlobalISel] Select floor and ceil (authored by Petar.Avramovic). · Explain WhyJun 6 2019, 2:00 AM
This revision was automatically updated to reflect the committed changes.
Petar.Avramovic marked 2 inline comments as done.Jun 6 2019, 2:03 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
GlobalISel/
10 lines
Target/
Mips/
3 lines
test/
CodeGen/
Mips/
GlobalISel/
legalizer/
147 lines
llvm-ir/
79 lines

Diff 203308

llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 268 Lines • ▼ Show 20 Linesstatic RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
case TargetOpcode::G_FLOG: case TargetOpcode::G_FLOG:
assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size"); assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
return Size == 128 ? RTLIB::LOG_F128 return Size == 128 ? RTLIB::LOG_F128
: Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32; : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
case TargetOpcode::G_FLOG2: case TargetOpcode::G_FLOG2:
assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size"); assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
return Size == 128 ? RTLIB::LOG2_F128 return Size == 128 ? RTLIB::LOG2_F128
: Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32; : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
case TargetOpcode::G_FCEIL:
assert((Size == 32 || Size == 64) && "Unsupported size");
return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
case TargetOpcode::G_FFLOOR:
assert((Size == 32 || Size == 64) && "Unsupported size");
return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
} }
llvm_unreachable("Unknown libcall function"); llvm_unreachable("Unknown libcall function");
} }
LegalizerHelper::LegalizeResult LegalizerHelper::LegalizeResult
llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
const CallLowering::ArgInfo &Result, const CallLowering::ArgInfo &Result,
ArrayRef<CallLowering::ArgInfo> Args) { ArrayRef<CallLowering::ArgInfo> Args) {
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 LinesLegalizerHelper::libcall(MachineInstr &MI) {
case TargetOpcode::G_FPOW: case TargetOpcode::G_FPOW:
case TargetOpcode::G_FREM: case TargetOpcode::G_FREM:
case TargetOpcode::G_FCOS: case TargetOpcode::G_FCOS:
case TargetOpcode::G_FSIN: case TargetOpcode::G_FSIN:
case TargetOpcode::G_FLOG10: case TargetOpcode::G_FLOG10:
case TargetOpcode::G_FLOG: case TargetOpcode::G_FLOG:
case TargetOpcode::G_FLOG2: case TargetOpcode::G_FLOG2:
case TargetOpcode::G_FEXP: case TargetOpcode::G_FEXP:
case TargetOpcode::G_FEXP2: { case TargetOpcode::G_FEXP2:
case TargetOpcode::G_FCEIL:
case TargetOpcode::G_FFLOOR: {
if (Size > 64) { if (Size > 64) {
LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n"); LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
return UnableToLegalize; return UnableToLegalize;
} }
Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx); Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
if (Status != Legalized) if (Status != Legalized)
return Status; return Status;
▲ Show 20 Lines • Show All 2,721 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV}) getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
.legalFor({s32, s64}); .legalFor({s32, s64});
getActionDefinitionsBuilder(G_FCMP) getActionDefinitionsBuilder(G_FCMP)
.legalFor({{s32, s32}, {s32, s64}}) .legalFor({{s32, s32}, {s32, s64}})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
.libcallFor({s32, s64});
computeTables(); computeTables();
verify(*ST.getInstrInfo()); verify(*ST.getInstrInfo());
} }
bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI, bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
MachineRegisterInfo &MRI, MachineRegisterInfo &MRI,
MachineIRBuilder &MIRBuilder, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const { GISelChangeObserver &Observer) const {
using namespace TargetOpcode; using namespace TargetOpcode;
MIRBuilder.setInstr(MI); MIRBuilder.setInstr(MI);
return false; return false;
} }

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @ceil_f32() {entry: ret void}
define void @ceil_f64() {entry: ret void}
define void @floor_f32() {entry: ret void}
define void @floor_f64() {entry: ret void}
...
---
name: ceil_f32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: ceil_f32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $f12 = COPY [[COPY]](s32)
; FP32: JAL &ceilf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $f0 = COPY [[COPY1]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: ceil_f32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $f12 = COPY [[COPY]](s32)
; FP64: JAL &ceilf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $f0 = COPY [[COPY1]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = COPY $f12
%1:_(s32) = G_FCEIL %0
$f0 = COPY %1(s32)
RetRA implicit $f0
...
---
name: ceil_f64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: ceil_f64
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $d6 = COPY [[COPY]](s64)
; FP32: JAL &ceil, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $d0
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $d0 = COPY [[COPY1]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: ceil_f64
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $d12_64 = COPY [[COPY]](s64)
; FP64: JAL &ceil, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $d0_64
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $d0 = COPY [[COPY1]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = COPY $d6
%1:_(s64) = G_FCEIL %0
$d0 = COPY %1(s64)
RetRA implicit $d0
...
---
name: floor_f32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: floor_f32
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $f12 = COPY [[COPY]](s32)
; FP32: JAL &floorf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $f0 = COPY [[COPY1]](s32)
; FP32: RetRA implicit $f0
; FP64-LABEL: name: floor_f32
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $f12 = COPY [[COPY]](s32)
; FP64: JAL &floorf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $f0 = COPY [[COPY1]](s32)
; FP64: RetRA implicit $f0
%0:_(s32) = COPY $f12
%1:_(s32) = G_FFLOOR %0
$f0 = COPY %1(s32)
RetRA implicit $f0
...
---
name: floor_f64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: floor_f64
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP32: $d6 = COPY [[COPY]](s64)
; FP32: JAL &floor, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $d0
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP32: $d0 = COPY [[COPY1]](s64)
; FP32: RetRA implicit $d0
; FP64-LABEL: name: floor_f64
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; FP64: $d12_64 = COPY [[COPY]](s64)
; FP64: JAL &floor, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $d0_64
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64
; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; FP64: $d0 = COPY [[COPY1]](s64)
; FP64: RetRA implicit $d0
%0:_(s64) = COPY $d6
%1:_(s64) = G_FFLOOR %0
$d0 = COPY %1(s64)
RetRA implicit $d0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
declare float @llvm.ceil.f32(float)
define float @ceil_f32(float %a) {
; MIPS32-LABEL: ceil_f32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal ceilf
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%0 = call float @llvm.ceil.f32(float %a)
ret float %0
}
declare double @llvm.ceil.f64(double)
define double @ceil_f64(double %a) {
; MIPS32-LABEL: ceil_f64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal ceil
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%0 = call double @llvm.ceil.f64(double %a)
ret double %0
}
declare float @llvm.floor.f32(float)
define float @floor_f32(float %a) {
; MIPS32-LABEL: floor_f32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal floorf
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%0 = call float @llvm.floor.f32(float %a)
ret float %0
}
declare double @llvm.floor.f64(double)
define double @floor_f64(double %a) {
; MIPS32-LABEL: floor_f64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: jal floor
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
%0 = call double @llvm.floor.f64(double %a)
ret double %0
}