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Differential D62900

[RISCV] Support Bit-Preserving FP in F/D Extensions
ClosedPublic

Authored by lenary on Jun 5 2019, 6:52 AM.

Details

Reviewers
asb
luismarques
Commits
rGf720647ddd71: [RISCV] Support Bit-Preserving FP in F/D Extensions
rL362790: [RISCV] Support Bit-Preserving FP in F/D Extensions
Summary

This allows some integer bitwise operations to instead be performed by
hardware fp instructions. This is correct because the RISC-V spec
requires the F and D extensions to use the IEEE-754 standard
representation, and fp register loads and stores to be bit-preserving.

This is tested against the soft-float ABI, but with hardware float
extensions enabled, so that the tests also ensure the optimisation also
fires in this case.

Diff Detail

Event Timeline

lenary created this revision.Jun 5 2019, 6:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 5 2019, 6:52 AM
Herald added subscribers: llvm-commits, Jim, benna and 20 others. · View Herald Transcript
Harbormaster completed remote builds in B32928: Diff 203135.Jun 5 2019, 6:52 AM
lenary updated this revision to Diff 203137.Jun 5 2019, 6:55 AM
  • Update Testcase Comment
Harbormaster completed remote builds in B32929: Diff 203137.Jun 5 2019, 6:55 AM
asb accepted this revision.Jun 5 2019, 9:56 PM

With the addition of nounwind to the tests, this looks good to me. Thanks!

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
18

Please add the nounwind attribute to all of these functions, so this tests won't be affected when call frame info directives are emitted (update_llc_test_checks.py doesn't strip them out).

This revision is now accepted and ready to land.Jun 5 2019, 9:56 PM
lenary updated this revision to Diff 203317.Jun 6 2019, 2:47 AM
  • Add nounwind directives to testcases
lenary marked 2 inline comments as done.Jun 6 2019, 2:47 AM
lenary added inline comments.
llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
18

Sure, done!

lenary marked an inline comment as done.Jun 6 2019, 2:48 AM
Harbormaster completed remote builds in B32981: Diff 203317.Jun 6 2019, 2:50 AM
Closed by commit rL362790: [RISCV] Support Bit-Preserving FP in F/D Extensions (authored by lenary). · Explain WhyJun 7 2019, 5:18 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
5 lines
test/
CodeGen/
RISCV/
390 lines

Diff 203317

llvm/lib/Target/RISCV/RISCVISelLowering.h

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
Instruction *I = nullptr) const override; Instruction *I = nullptr) const override;
bool isLegalICmpImmediate(int64_t Imm) const override; bool isLegalICmpImmediate(int64_t Imm) const override;
bool isLegalAddImmediate(int64_t Imm) const override; bool isLegalAddImmediate(int64_t Imm) const override;
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
bool isZExtFree(SDValue Val, EVT VT2) const override; bool isZExtFree(SDValue Val, EVT VT2) const override;
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override; bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
bool hasBitPreservingFPLogic(EVT VT) const override;
// Provide custom lowering hooks for some operations. // Provide custom lowering hooks for some operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const override; SelectionDAG &DAG) const override;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Show First 20 Lines • Show All 296 Lines • ▼ Show 20 Linesbool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
return TargetLowering::isZExtFree(Val, VT2); return TargetLowering::isZExtFree(Val, VT2);
} }
bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
} }
bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
return (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
(VT == MVT::f64 && Subtarget.hasStdExtD());
}
// Changes the condition code and swaps operands if necessary, so the SetCC // Changes the condition code and swaps operands if necessary, so the SetCC
// operation matches one of the comparisons supported directly in the RISC-V // operation matches one of the comparisons supported directly in the RISC-V
// ISA. // ISA.
static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
switch (CC) { switch (CC) {
default: default:
break; break;
case ISD::SETGT: case ISD::SETGT:
▲ Show 20 Lines • Show All 1,992 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32FD %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64FD %s
; These functions perform extra work to ensure that `%a3` starts in a
; floating-point register, if the machine has them, and the result of
; the bitwise operation is then needed in a floating-point register.
; This should mean the optimisations will fire even if you're using the
; soft-float ABI on a machine with hardware floating-point support.
define float @bitcast_and(float %a1, float %a2) nounwind {
; RV32F-LABEL: bitcast_and:
asbUnsubmitted
Done
ReplyInline Actions

Please add the nounwind attribute to all of these functions, so this tests won't be affected when call frame info directives are emitted (update_llc_test_checks.py doesn't strip them out).

asb: Please add the `nounwind` attribute to all of these functions, so this tests won't be affected…
lenaryAuthorUnsubmitted
Done
ReplyInline Actions

Sure, done!

lenary: Sure, done!
; RV32F: # %bb.0:
; RV32F-NEXT: fmv.w.x ft0, a1
; RV32F-NEXT: fmv.w.x ft1, a0
; RV32F-NEXT: fadd.s ft0, ft1, ft0
; RV32F-NEXT: fabs.s ft0, ft0
; RV32F-NEXT: fadd.s ft0, ft1, ft0
; RV32F-NEXT: fmv.x.w a0, ft0
; RV32F-NEXT: ret
;
; RV32FD-LABEL: bitcast_and:
; RV32FD: # %bb.0:
; RV32FD-NEXT: fmv.w.x ft0, a1
; RV32FD-NEXT: fmv.w.x ft1, a0
; RV32FD-NEXT: fadd.s ft0, ft1, ft0
; RV32FD-NEXT: fabs.s ft0, ft0
; RV32FD-NEXT: fadd.s ft0, ft1, ft0
; RV32FD-NEXT: fmv.x.w a0, ft0
; RV32FD-NEXT: ret
;
; RV64F-LABEL: bitcast_and:
; RV64F: # %bb.0:
; RV64F-NEXT: fmv.w.x ft0, a1
; RV64F-NEXT: fmv.w.x ft1, a0
; RV64F-NEXT: fadd.s ft0, ft1, ft0
; RV64F-NEXT: fabs.s ft0, ft0
; RV64F-NEXT: fadd.s ft0, ft1, ft0
; RV64F-NEXT: fmv.x.w a0, ft0
; RV64F-NEXT: ret
;
; RV64FD-LABEL: bitcast_and:
; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.w.x ft0, a1
; RV64FD-NEXT: fmv.w.x ft1, a0
; RV64FD-NEXT: fadd.s ft0, ft1, ft0
; RV64FD-NEXT: fabs.s ft0, ft0
; RV64FD-NEXT: fadd.s ft0, ft1, ft0
; RV64FD-NEXT: fmv.x.w a0, ft0
; RV64FD-NEXT: ret
%a3 = fadd float %a1, %a2
%bc1 = bitcast float %a3 to i32
%and = and i32 %bc1, 2147483647
%bc2 = bitcast i32 %and to float
%a4 = fadd float %a1, %bc2
ret float %a4
}
define double @bitcast_double_and(double %a1, double %a2) nounwind {
; RV32F-LABEL: bitcast_double_and:
; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw ra, 12(sp)
; RV32F-NEXT: sw s0, 8(sp)
; RV32F-NEXT: sw s1, 4(sp)
; RV32F-NEXT: mv s0, a1
; RV32F-NEXT: mv s1, a0
; RV32F-NEXT: call __adddf3
; RV32F-NEXT: mv a2, a0
; RV32F-NEXT: lui a0, 524288
; RV32F-NEXT: addi a0, a0, -1
; RV32F-NEXT: and a3, a1, a0
; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __adddf3
; RV32F-NEXT: lw s1, 4(sp)
; RV32F-NEXT: lw s0, 8(sp)
; RV32F-NEXT: lw ra, 12(sp)
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
; RV32FD-LABEL: bitcast_double_and:
; RV32FD: # %bb.0:
; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp)
; RV32FD-NEXT: fld ft0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp)
; RV32FD-NEXT: fld ft1, 8(sp)
; RV32FD-NEXT: fadd.d ft0, ft1, ft0
; RV32FD-NEXT: fabs.d ft0, ft0
; RV32FD-NEXT: fadd.d ft0, ft1, ft0
; RV32FD-NEXT: fsd ft0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16
; RV32FD-NEXT: ret
;
; RV64F-LABEL: bitcast_double_and:
; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp)
; RV64F-NEXT: sd s0, 0(sp)
; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __adddf3
; RV64F-NEXT: addi a1, zero, -1
; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: addi a1, a1, -1
; RV64F-NEXT: and a1, a0, a1
; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __adddf3
; RV64F-NEXT: ld s0, 0(sp)
; RV64F-NEXT: ld ra, 8(sp)
; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret
;
; RV64FD-LABEL: bitcast_double_and:
; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.d.x ft0, a1
; RV64FD-NEXT: fmv.d.x ft1, a0
; RV64FD-NEXT: fadd.d ft0, ft1, ft0
; RV64FD-NEXT: fabs.d ft0, ft0
; RV64FD-NEXT: fadd.d ft0, ft1, ft0
; RV64FD-NEXT: fmv.x.d a0, ft0
; RV64FD-NEXT: ret
%a3 = fadd double %a1, %a2
%bc1 = bitcast double %a3 to i64
%and = and i64 %bc1, 9223372036854775807
%bc2 = bitcast i64 %and to double
%a4 = fadd double %a1, %bc2
ret double %a4
}
define float @bitcast_xor(float %a1, float %a2) nounwind {
; RV32F-LABEL: bitcast_xor:
; RV32F: # %bb.0:
; RV32F-NEXT: fmv.w.x ft0, a1
; RV32F-NEXT: fmv.w.x ft1, a0
; RV32F-NEXT: fmul.s ft0, ft1, ft0
; RV32F-NEXT: fneg.s ft0, ft0
; RV32F-NEXT: fmul.s ft0, ft1, ft0
; RV32F-NEXT: fmv.x.w a0, ft0
; RV32F-NEXT: ret
;
; RV32FD-LABEL: bitcast_xor:
; RV32FD: # %bb.0:
; RV32FD-NEXT: fmv.w.x ft0, a1
; RV32FD-NEXT: fmv.w.x ft1, a0
; RV32FD-NEXT: fmul.s ft0, ft1, ft0
; RV32FD-NEXT: fneg.s ft0, ft0
; RV32FD-NEXT: fmul.s ft0, ft1, ft0
; RV32FD-NEXT: fmv.x.w a0, ft0
; RV32FD-NEXT: ret
;
; RV64F-LABEL: bitcast_xor:
; RV64F: # %bb.0:
; RV64F-NEXT: fmv.w.x ft0, a1
; RV64F-NEXT: fmv.w.x ft1, a0
; RV64F-NEXT: fmul.s ft0, ft1, ft0
; RV64F-NEXT: fneg.s ft0, ft0
; RV64F-NEXT: fmul.s ft0, ft1, ft0
; RV64F-NEXT: fmv.x.w a0, ft0
; RV64F-NEXT: ret
;
; RV64FD-LABEL: bitcast_xor:
; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.w.x ft0, a1
; RV64FD-NEXT: fmv.w.x ft1, a0
; RV64FD-NEXT: fmul.s ft0, ft1, ft0
; RV64FD-NEXT: fneg.s ft0, ft0
; RV64FD-NEXT: fmul.s ft0, ft1, ft0
; RV64FD-NEXT: fmv.x.w a0, ft0
; RV64FD-NEXT: ret
%a3 = fmul float %a1, %a2
%bc1 = bitcast float %a3 to i32
%and = xor i32 %bc1, 2147483648
%bc2 = bitcast i32 %and to float
%a4 = fmul float %a1, %bc2
ret float %a4
}
define double @bitcast_double_xor(double %a1, double %a2) nounwind {
; RV32F-LABEL: bitcast_double_xor:
; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw ra, 12(sp)
; RV32F-NEXT: sw s0, 8(sp)
; RV32F-NEXT: sw s1, 4(sp)
; RV32F-NEXT: mv s0, a1
; RV32F-NEXT: mv s1, a0
; RV32F-NEXT: call __muldf3
; RV32F-NEXT: mv a2, a0
; RV32F-NEXT: lui a0, 524288
; RV32F-NEXT: xor a3, a1, a0
; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __muldf3
; RV32F-NEXT: lw s1, 4(sp)
; RV32F-NEXT: lw s0, 8(sp)
; RV32F-NEXT: lw ra, 12(sp)
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
; RV32FD-LABEL: bitcast_double_xor:
; RV32FD: # %bb.0:
; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp)
; RV32FD-NEXT: fld ft0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp)
; RV32FD-NEXT: fld ft1, 8(sp)
; RV32FD-NEXT: fmul.d ft0, ft1, ft0
; RV32FD-NEXT: fneg.d ft0, ft0
; RV32FD-NEXT: fmul.d ft0, ft1, ft0
; RV32FD-NEXT: fsd ft0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16
; RV32FD-NEXT: ret
;
; RV64F-LABEL: bitcast_double_xor:
; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp)
; RV64F-NEXT: sd s0, 0(sp)
; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __muldf3
; RV64F-NEXT: addi a1, zero, -1
; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: xor a1, a0, a1
; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3
; RV64F-NEXT: ld s0, 0(sp)
; RV64F-NEXT: ld ra, 8(sp)
; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret
;
; RV64FD-LABEL: bitcast_double_xor:
; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.d.x ft0, a1
; RV64FD-NEXT: fmv.d.x ft1, a0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0
; RV64FD-NEXT: fneg.d ft0, ft0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0
; RV64FD-NEXT: fmv.x.d a0, ft0
; RV64FD-NEXT: ret
%a3 = fmul double %a1, %a2
%bc1 = bitcast double %a3 to i64
%and = xor i64 %bc1, 9223372036854775808
%bc2 = bitcast i64 %and to double
%a4 = fmul double %a1, %bc2
ret double %a4
}
define float @bitcast_or(float %a1, float %a2) nounwind {
; RV32F-LABEL: bitcast_or:
; RV32F: # %bb.0:
; RV32F-NEXT: fmv.w.x ft0, a1
; RV32F-NEXT: fmv.w.x ft1, a0
; RV32F-NEXT: fmul.s ft0, ft1, ft0
; RV32F-NEXT: fabs.s ft0, ft0
; RV32F-NEXT: fneg.s ft0, ft0
; RV32F-NEXT: fmul.s ft0, ft1, ft0
; RV32F-NEXT: fmv.x.w a0, ft0
; RV32F-NEXT: ret
;
; RV32FD-LABEL: bitcast_or:
; RV32FD: # %bb.0:
; RV32FD-NEXT: fmv.w.x ft0, a1
; RV32FD-NEXT: fmv.w.x ft1, a0
; RV32FD-NEXT: fmul.s ft0, ft1, ft0
; RV32FD-NEXT: fabs.s ft0, ft0
; RV32FD-NEXT: fneg.s ft0, ft0
; RV32FD-NEXT: fmul.s ft0, ft1, ft0
; RV32FD-NEXT: fmv.x.w a0, ft0
; RV32FD-NEXT: ret
;
; RV64F-LABEL: bitcast_or:
; RV64F: # %bb.0:
; RV64F-NEXT: fmv.w.x ft0, a1
; RV64F-NEXT: fmv.w.x ft1, a0
; RV64F-NEXT: fmul.s ft0, ft1, ft0
; RV64F-NEXT: fabs.s ft0, ft0
; RV64F-NEXT: fneg.s ft0, ft0
; RV64F-NEXT: fmul.s ft0, ft1, ft0
; RV64F-NEXT: fmv.x.w a0, ft0
; RV64F-NEXT: ret
;
; RV64FD-LABEL: bitcast_or:
; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.w.x ft0, a1
; RV64FD-NEXT: fmv.w.x ft1, a0
; RV64FD-NEXT: fmul.s ft0, ft1, ft0
; RV64FD-NEXT: fabs.s ft0, ft0
; RV64FD-NEXT: fneg.s ft0, ft0
; RV64FD-NEXT: fmul.s ft0, ft1, ft0
; RV64FD-NEXT: fmv.x.w a0, ft0
; RV64FD-NEXT: ret
%a3 = fmul float %a1, %a2
%bc1 = bitcast float %a3 to i32
%and = or i32 %bc1, 2147483648
%bc2 = bitcast i32 %and to float
%a4 = fmul float %a1, %bc2
ret float %a4
}
define double @bitcast_double_or(double %a1, double %a2) nounwind {
; RV32F-LABEL: bitcast_double_or:
; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw ra, 12(sp)
; RV32F-NEXT: sw s0, 8(sp)
; RV32F-NEXT: sw s1, 4(sp)
; RV32F-NEXT: mv s0, a1
; RV32F-NEXT: mv s1, a0
; RV32F-NEXT: call __muldf3
; RV32F-NEXT: mv a2, a0
; RV32F-NEXT: lui a0, 524288
; RV32F-NEXT: or a3, a1, a0
; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __muldf3
; RV32F-NEXT: lw s1, 4(sp)
; RV32F-NEXT: lw s0, 8(sp)
; RV32F-NEXT: lw ra, 12(sp)
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
; RV32FD-LABEL: bitcast_double_or:
; RV32FD: # %bb.0:
; RV32FD-NEXT: addi sp, sp, -16
; RV32FD-NEXT: sw a2, 8(sp)
; RV32FD-NEXT: sw a3, 12(sp)
; RV32FD-NEXT: fld ft0, 8(sp)
; RV32FD-NEXT: sw a0, 8(sp)
; RV32FD-NEXT: sw a1, 12(sp)
; RV32FD-NEXT: fld ft1, 8(sp)
; RV32FD-NEXT: fmul.d ft0, ft1, ft0
; RV32FD-NEXT: fabs.d ft0, ft0
; RV32FD-NEXT: fneg.d ft0, ft0
; RV32FD-NEXT: fmul.d ft0, ft1, ft0
; RV32FD-NEXT: fsd ft0, 8(sp)
; RV32FD-NEXT: lw a0, 8(sp)
; RV32FD-NEXT: lw a1, 12(sp)
; RV32FD-NEXT: addi sp, sp, 16
; RV32FD-NEXT: ret
;
; RV64F-LABEL: bitcast_double_or:
; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp)
; RV64F-NEXT: sd s0, 0(sp)
; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __muldf3
; RV64F-NEXT: addi a1, zero, -1
; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: or a1, a0, a1
; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3
; RV64F-NEXT: ld s0, 0(sp)
; RV64F-NEXT: ld ra, 8(sp)
; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret
;
; RV64FD-LABEL: bitcast_double_or:
; RV64FD: # %bb.0:
; RV64FD-NEXT: fmv.d.x ft0, a1
; RV64FD-NEXT: fmv.d.x ft1, a0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0
; RV64FD-NEXT: fabs.d ft0, ft0
; RV64FD-NEXT: fneg.d ft0, ft0
; RV64FD-NEXT: fmul.d ft0, ft1, ft0
; RV64FD-NEXT: fmv.x.d a0, ft0
; RV64FD-NEXT: ret
%a3 = fmul double %a1, %a2
%bc1 = bitcast double %a3 to i64
%and = or i64 %bc1, 9223372036854775808
%bc2 = bitcast i64 %and to double
%a4 = fmul double %a1, %bc2
ret double %a4
}