Workaround for PR41575: don't allow inlining of clear_cache on some platforms

[george.burgess.iv]

Summary

As detailed in https://llvm.org/PR41575, this code shouldn't be relying on implicit saves/restores for the registers it uses __asm("rN") on. There are a few ways forward with this, but until we land one of those, the ARM function call ABI appears to save us here. No pun intended. :)

[george.burgess.iv]

ping :)

compiler-rt/lib/builtins/clear_cache.c

 #endif
 #endif
 
 // The compiler generates calls to __clear_cache() when creating
 // trampoline functions on the stack for use with nested functions.
 // It is expected to invalidate the instruction cache for the
 // specified range.
 
+// PR41575: The implicit clobber of r7 here doesn't play nicely with inlining.
+// Until we determine a better way to fix that, this shouldn't be inlined.
+#if defined(__arm__) && defined(__linux__)
+NOINLINE
+#endif
 void __clear_cache(void *start, void *end) {
 #if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64)
 // Intel processors have a unified instruction and data cache
 // so there is nothing to do
 #elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__))
   FlushInstructionCache(GetCurrentProcess(), start, end - start);
 #elif defined(__arm__) && !defined(__APPLE__)
 #if defined(__FreeBSD__) || defined(__NetBSD__)