[mips] Add assembler support for the .cprestore directive.

[dsanders]

Summary

This assembler directive is used in O32 PIC to restore the current function's $gp after executing JAL's. The $gp is first stored on the stack at a user-specified offset.
It has the following format: ".cprestore 8" (where 8 is the offset).

This fixes llvm.org/PR20967.

[tomatabacu]

Ping.

[tomatabacu]

Ping 2.

[tomatabacu]

Ping 3.

[emaste]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1730–1731

According to http://techpubs.sgi.com/library/dynaweb_docs/0530/SGI_Developer/books/Cplr_PTG/sgi_html/apa.html .cprestore should be a silent nop in non-PIC mode so that the same assembly source can be used in both PIC and non-PIC mode.

[tomatabacu]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1730–1731

I know what you mean, but I believe you've highlighted the wrong code.
The warning we were talking about on Bugzilla is for using .cprestore in non-PIC mode (MipsAsmParser.cpp at 3373-3374), but the warning you've highlighted here is for *not* using .cprestore *in* PIC mode.

[tomatabacu]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1730–1731

Forgot to mention that the warning highlighted here is also implemented in GAS.

[tomatabacu]

Removed 2 warnings which were considered too strict (as discussed in llvm.org/PR20967).
Updated checks for the N32 and N64 ABIs in MipsTargetELFStreamer.
Updated tests because the microMIPS disassembler got fixed.
Rebased.

[emaste]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1730–1731

You're right, of course. I just wanted to make sure the comment was in the review and grabbed the wrong warning.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

399

Just to be on the safe side, could you also initialize CpRestoreOffset in the constructor?

1531

Nit: if(!ExpandedJalSym)

1727–1761

I'm a bit confused by this code. Emitting a nop after a jal/jalr/jalrs makes sense to me, but I don't understand why the presence of the nop depends on inPicMode() and (!N32 && !N64).

I'm also not sure why the non-macro versions of jalr/jalrs (which set ExpandedJalSym to true) are causing createCpRestoreMemOp() to be called.

1731

This comment isn't quite right. It's emitting a nop if we are in '.set noreorder' mode.

1879–1880

We ought to factor out the nop emission at some point

[tomatabacu]

Replied to an inline comment.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1879–1880

Done in http://reviews.llvm.org/D8320. I'd rather wait until that gets committed before I update this one, instead of juggling around with all these patches.

[tomatabacu]

Addressed review comments.
Fixed duplicate emission of JALR when expanding a "JAL symbol".
Removed redundant test cases.
Added NOT checks.
Cleaned up tests.

[tomatabacu]

Replied to inline comments.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

399

Done.

1531

Actually found a bug with this, so the "if" you commented about no longer exists, but I addressed the nit for the new code.

1727–1761

.cprestore causes an LW of $gp to be emitted after an expanded "JAL symbol" (which becomes a JALR) and it does so only if we're in PIC mode and using the O32 ABI. Between that JALR and the LW, we emit a NOP, which will have the same dependencies as .cprestore.

In response to your 2nd comment, AFAICT, ExpandedJalSym is true only if we did the PIC expansion for a "JAL symbol".

1731

Fixed.

1879–1880

Fully done.

[dsanders]

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1727–1761

.cprestore causes an LW of $gp to be emitted after an expanded "JAL symbol" (which becomes a JALR) and it does so only if we're in PIC mode
and using the O32 ABI. Between that JALR and the LW, we emit a NOP, which will have the same dependencies as .cprestore.

Ah ok. So it's true when .cprestore has a visible effect on the output and false otherwise. That makes sense to me. In that case I'd suggest using inline functions to give this condition a more meaningful name (maybe shouldCprestoreModifyJal() or shouldRestoreGPAfterJal()?).

In response to your 2nd comment, AFAICT, ExpandedJalSym is true only if we did the PIC expansion for a "JAL symbol".

I see where my confusion is. jal is a macro that potentially expands to the jal instruction (or a sequence involving the jal instruction) and we're using the tablegen-erated assembly parsing for the jal instruction to parse the jal macro. The parsing gives us an MCInst which is the jal instruction but we expand it as if it were the jal macro to produce a jal instruction (or a sequence involving the jal instruction). Simple as that :-). It's a consequence of having the assembler and codegen in the same source which makes it difficult to separate the overlapping jal syntax. As confusing as it is, I can't think of a better way to go about it at the moment. I think we should comment on how this expansion works and how the line between instructions and macros are a bit blurry somewhere (the start of this if-statement?) and try to resolve the confusion later. Maybe, we can do something involving isCodeGenOnly and a assembler-only pseudo.

By the way, I've just noticed that we don't seem to be honouring '.set nomacro' properly. At least, I don't seem to be able to find any suitable guards near/in needsExpansion() and expandInstruction(). If we aren't honoring it then -fintegrated-as is likely to emit different objects for assembling via temporary assembly files and directly from codegen. Our codegen uses '.set nomacro' so we should fix this soon.

[tomatabacu]

Rebased.

[tomatabacu]

Rebased (for Sean Bruno's convenience).

[dsanders]

It's been a while since I reviewed this but I saw you'd rebased it again and took another look. I believe we had resolved almost all the issues and I was just waiting for a fairly minor change (see the shouldCprestoreModifyJal() comment).

[tomatabacu]

Outlined the (inPicMode() && !(isABI_N32() || isABI_N64())) condition into a separate function.
Switched to using !isInt<16>() in createCpRestoreMemOp() if condition.
Moved forbidModuleDirective() calls to the MipsTargetStreamer base class.
Removed redundant addition to the .set reorder NOP-creation condition.
Improved code comments to better explain why we need a NOP after the JALR in .set noreorder.

I believe this addresses all the remaining review comments for this patch.

[dsanders]

LGTM with a couple nits and a more concept-focused spelling for the new predicate.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

1735

This spelling says the same thing as the condition did. The intent was to name the predicate after the concept being tested rather than the mechanical values being tested.

1751–1753

Nit: Redundant braces.

2396–2399

Nit: Use ternary operator

[seanbruno]

Thanks for the work on this!

[dsanders]

Thanks for triggering an email on this thread. It wasn't on my list of patches to commandeer when Toma finished his placement.

I'll fix the remaining nits and get this committed.

[seanbruno]

Seems to still apply (and FreeBSD needs it to build our mips/mips64 targets).

[dsanders]

Apologies for the delay on this. I had it ready to commit a few weeks ago but it seems I never actually committed it.

I'm re-building and re-testing now and will commit shortly assuming the tests pass.

[dsanders]

Committed in r247897

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

class MipsAsmParser : public MCTargetAsmParser {
   MCSubtargetInfo &STI;
   MipsABIInfo ABI;
   SmallVector<std::unique_ptr<MipsAssemblerOptions>, 2> AssemblerOptions;
   MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a
                        // nullptr, which indicates that no function is currently
                        // selected. This usually happens after an '.end func'
                        // directive.
   bool IsPicEnabled;
+  bool IsCpRestoreSet;
+  int CpRestoreOffset;
 
   // Print a warning along with its fix-it message at the given range.
   void printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg,
                              SMRange Range, bool ShowColors = true);
 
 #define GET_ASSEMBLER_HEADER
 #include "MipsGenAsmMatcher.inc"
 
bool expandBranchImm(MCInst &Inst, SMLoc IDLoc,
                        SmallVectorImpl<MCInst> &Instructions);
 
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
   void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
                   SmallVectorImpl<MCInst> &Instructions);
 
+  void createCpRestoreMemOp(bool IsLoad, int StackOffset, SMLoc IDLoc,
+                            SmallVectorImpl<MCInst> &Instructions);
+
   bool reportParseError(Twine ErrorMsg);
   bool reportParseError(SMLoc Loc, Twine ErrorMsg);
 
   bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
   bool parseRelocOperand(const MCExpr *&Res);
 
   const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
 
   bool isEvaluated(const MCExpr *Expr);
   bool parseSetMips0Directive();
   bool parseSetArchDirective();
   bool parseSetFeature(uint64_t Feature);
   bool parseDirectiveCpLoad(SMLoc Loc);
+  bool parseDirectiveCpRestore(SMLoc Loc);
   bool parseDirectiveCPSetup();
   bool parseDirectiveNaN();
   bool parseDirectiveSet();
   bool parseDirectiveOption();
   bool parseInsnDirective();
 
   bool parseSetAtDirective();
   bool parseSetNoAtDirective();
MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
 
     if (!isABI_O32() && !useOddSPReg() != 0)
       report_fatal_error("-mno-odd-spreg requires the O32 ABI");
 
     CurrentFn = nullptr;
 
     IsPicEnabled =
         (getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_);
+
+    IsCpRestoreSet = false;
+    CpRestoreOffset = -1;
   }
 
   /// True if all of $fcc0 - $fcc7 exist for the current ISA.
   bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
 
   bool isGP64bit() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
   bool isFP64bit() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
   const MipsABIInfo &getABI() const { return ABI; }
switch (Opcode) {
     default:
       return false;
   }
 }
 
 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
                                        SmallVectorImpl<MCInst> &Instructions) {
   const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
+  bool ExpandedJalSym = false;
 
   Inst.setLoc(IDLoc);
 
   if (MCID.isBranch() || MCID.isCall()) {
     const unsigned Opcode = Inst.getOpcode();
     MCOperand Offset;
 
     switch (Opcode) {
if (JalSym->isInSection() || JalSym->isTemporary()) {
 
       // Create the R_(MICRO)MIPS_CALL16 relocation.
       const MCExpr *Call16RelocExpr = evaluateRelocExpr(JalExpr, "call16");
       LoadInst.addOperand(MCOperand::createExpr(Call16RelocExpr));
       Instructions.push_back(LoadInst);
     }
 
     MCInst JalrInst;
+    if (IsCpRestoreSet && inMicroMipsMode())
+      JalrInst.setOpcode(Mips::JALRS_MM);
+    else
       JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
     JalrInst.addOperand(MCOperand::createReg(Mips::RA));
     JalrInst.addOperand(MCOperand::createReg(Mips::T9));
 
     // FIXME: Add an R_(MICRO)MIPS_JALR relocation after the JALR.
     // This relocation is supposed to be an optimization hint for the linker
     // and is not necessary for correctness.
 
     Inst = JalrInst;
+    ExpandedJalSym = true;
   }
 
   if (MCID.mayLoad() || MCID.mayStore()) {
     // Check the offset of memory operand, if it is a symbol
     // reference or immediate we may have to expand instructions.
     for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
       const MCOperandInfo &OpInfo = MCID.OpInfo[i];
       if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
           (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
         MCOperand &Op = Inst.getOperand(i);
         if (Op.isImm()) {
bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
 
   if (needsExpansion(Inst)) {
     if (expandInstruction(Inst, IDLoc, Instructions))
       return true;
   } else
     Instructions.push_back(Inst);
 
   // If this instruction has a delay slot and .set reorder is active,
   // emit a NOP after it.
-  if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
+  // @Fixme? ExpandedJalSym
+  if ((MCID.hasDelaySlot() || ExpandedJalSym) &&
+      AssemblerOptions.back()->isReorder())
     createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Instructions);
 
+  if ((Inst.getOpcode() == Mips::JalOneReg ||
+       Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) &&
+      inPicMode() && !(isABI_N32() || isABI_N64())) {
+    if (IsCpRestoreSet) {
+      // If .set noreorder has been used, emit a NOP after the generated JALR.
+      // If .set reorder has been used, we've already emitted the NOP.
+      if (!AssemblerOptions.back()->isReorder())
+        createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Instructions);
+
+      // Load the $gp from the stack.
+      SmallVector<MCInst, 3> LoadInsts;
+      createCpRestoreMemOp(true /*IsLoad*/, CpRestoreOffset /*StackOffset*/,
+                           IDLoc, LoadInsts);
+
+      for (const MCInst &Inst : LoadInsts)
+        Instructions.push_back(Inst);
+
+    } else {
+      Warning(IDLoc, "no .cprestore used in PIC mode");
+    }
+  }
+
   return false;
 }
 
 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
 
   switch (Inst.getOpcode()) {
   case Mips::LoadImm32:
   case Mips::LoadImm64:
   case Mips::LoadAddrImm32:
   case Mips::LoadAddrReg32:
   case Mips::B_MM_Pseudo:
   case Mips::LWM_MM:
   case Mips::SWM_MM:
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
   // Create a JALR instruction which is going to replace the pseudo-JAL.
   MCInst JalrInst;
   JalrInst.setLoc(IDLoc);
   const MCOperand FirstRegOp = Inst.getOperand(0);
   const unsigned Opcode = Inst.getOpcode();
 
   if (Opcode == Mips::JalOneReg) {
     // jal $rs => jalr $rs
-    if (inMicroMipsMode()) {
+    if (IsCpRestoreSet && inMicroMipsMode()) {
+      JalrInst.setOpcode(Mips::JALRS16_MM);
+      JalrInst.addOperand(FirstRegOp);
+    } else if (inMicroMipsMode()) {
       JalrInst.setOpcode(Mips::JALR16_MM);
       JalrInst.addOperand(FirstRegOp);
     } else {
       JalrInst.setOpcode(Mips::JALR);
       JalrInst.addOperand(MCOperand::createReg(Mips::RA));
       JalrInst.addOperand(FirstRegOp);
     }
   } else if (Opcode == Mips::JalTwoReg) {
     // jal $rd, $rs => jalr $rd, $rs
+    if (IsCpRestoreSet && inMicroMipsMode())
+      JalrInst.setOpcode(Mips::JALRS_MM);
+    else
       JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
     JalrInst.addOperand(FirstRegOp);
     const MCOperand SecondRegOp = Inst.getOperand(1);
     JalrInst.addOperand(SecondRegOp);
   }
   Instructions.push_back(JalrInst);
 
   // If .set reorder is active, emit a NOP after it.
-  if (AssemblerOptions.back()->isReorder()) {
-    // This is a 32-bit NOP because these 2 pseudo-instructions
-    // do not have a short delay slot.
-    MCInst NopInst;
-    NopInst.setOpcode(Mips::SLL);
-    NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
-    NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
-    NopInst.addOperand(MCOperand::createImm(0));
-    Instructions.push_back(NopInst);
-  }
+  if (AssemblerOptions.back()->isReorder())
+    createNop(hasShortDelaySlot(JalrInst.getOpcode()), IDLoc, Instructions);
 
   return false;
 }
 
 bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
                                   unsigned SrcReg, bool Is32BitImm, SMLoc IDLoc,
                                   SmallVectorImpl<MCInst> &Instructions) {
   if (!Is32BitImm && !isGP64bit()) {
void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg,
   MCInst AdduInst;
   AdduInst.setOpcode(Mips::ADDu);
   AdduInst.addOperand(MCOperand::createReg(DstReg));
   AdduInst.addOperand(MCOperand::createReg(SrcReg));
   AdduInst.addOperand(MCOperand::createReg(TrgReg));
   Instructions.push_back(AdduInst);
 }
 
+void MipsAsmParser::createCpRestoreMemOp(
+    bool IsLoad, int StackOffset, SMLoc IDLoc,
+    SmallVectorImpl<MCInst> &Instructions) {
+  MCInst MemInst;
+  if (IsLoad)
+    MemInst.setOpcode(Mips::LW);
+  else
+    MemInst.setOpcode(Mips::SW);
+
+  MemInst.addOperand(MCOperand::createReg(Mips::GP));
+  MemInst.addOperand(MCOperand::createReg(Mips::SP));
+  MemInst.addOperand(MCOperand::createImm(StackOffset));
+
+  // If the offset can not fit into 16 bits, we need to expand.
+  if (StackOffset < -32768 || StackOffset > 32767)
+    expandMemInst(MemInst, IDLoc, Instructions, IsLoad, true /*HasImmOpnd*/);
+  else
+    Instructions.push_back(MemInst);
+}
+
 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   // As described by the Mips32r2 spec, the registers Rd and Rs for
   // jalr.hb must be different.
   unsigned Opcode = Inst.getOpcode();
 
   if (Opcode == Mips::JALR_HB &&
       (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()))
     return Match_RequiresDifferentSrcAndDst;
if (getLexer().isNot(AsmToken::EndOfStatement)) {
     reportParseError("unexpected token, expected end of statement");
     return false;
   }
 
   getTargetStreamer().emitDirectiveCpLoad(RegOpnd.getGPR32Reg());
   return false;
 }
 
+bool MipsAsmParser::parseDirectiveCpRestore(SMLoc Loc) {
+  MCAsmParser &Parser = getParser();
+
+  // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
+  // is used in non-PIC mode.
+
+  if (inMips16Mode()) {
+    reportParseError(".cprestore is not supported in Mips16 mode");
+    return false;
+  }
+
+  // Get the stack offset value.
+  const MCExpr *StackOffset;
+  int64_t StackOffsetVal;
+  if (Parser.parseExpression(StackOffset)) {
+    reportParseError("expected stack offset value");
+    return false;
+  }
+
+  if (!StackOffset->evaluateAsAbsolute(StackOffsetVal)) {
+    reportParseError("stack offset is not an absolute expression");
+    return false;
+  }
+
+  if (StackOffsetVal < 0) {
+    Warning(Loc, ".cprestore with negative stack offset has no effect");
+    IsCpRestoreSet = false;
+  } else {
+    IsCpRestoreSet = true;
+    CpRestoreOffset = StackOffsetVal;
+  }
+
+  // If this is not the end of the statement, report an error.
+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
+    reportParseError("unexpected token, expected end of statement");
+    return false;
+  }
+
+  // Store the $gp on the stack.
+  SmallVector<MCInst, 3> StoreInsts;
+  createCpRestoreMemOp(false /*IsLoad*/, CpRestoreOffset /*StackOffset*/, Loc,
+                       StoreInsts);
+
+  getTargetStreamer().emitDirectiveCpRestore(StoreInsts, CpRestoreOffset);
+  Parser.Lex(); // Consume the EndOfStatement.
+  return false;
+}
+
 bool MipsAsmParser::parseDirectiveCPSetup() {
   MCAsmParser &Parser = getParser();
   unsigned FuncReg;
   unsigned Save;
   bool SaveIsReg = true;
 
   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
   OperandMatchResultTy ResTy = parseAnyRegister(TmpReg);

 }
 
 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
   MCAsmParser &Parser = getParser();
   StringRef IDVal = DirectiveID.getString();
 
   if (IDVal == ".cpload")
     return parseDirectiveCpLoad(DirectiveID.getLoc());
+  if (IDVal == ".cprestore")
+    return parseDirectiveCpRestore(DirectiveID.getLoc());
   if (IDVal == ".dword") {
     parseDataDirective(8, DirectiveID.getLoc());
     return false;
   }
   if (IDVal == ".ent") {
     StringRef SymbolName;
 
     if (Parser.parseIdentifier(SymbolName)) {
if (getLexer().isNot(AsmToken::EndOfStatement)) {
       reportParseError("unexpected token, expected end of statement");
       return false;
     }
 
     MCSymbol *Sym = getContext().getOrCreateSymbol(SymbolName);
 
     getTargetStreamer().emitDirectiveEnt(*Sym);
     CurrentFn = Sym;
+    IsCpRestoreSet = false;
     return false;
   }
 
   if (IDVal == ".end") {
     StringRef SymbolName;
 
     if (Parser.parseIdentifier(SymbolName)) {
       reportParseError("expected identifier after .end");
if (IDVal == ".end") {
 
     if ((SymbolName != CurrentFn->getName())) {
       reportParseError(".end symbol does not match .ent symbol");
       return false;
     }
 
     getTargetStreamer().emitDirectiveEnd(SymbolName);
     CurrentFn = nullptr;
+    IsCpRestoreSet = false;
     return false;
   }
 
   if (IDVal == ".frame") {
     // .frame $stack_reg, frame_size_in_bytes, $return_reg
     SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
     OperandMatchResultTy ResTy = parseAnyRegister(TmpReg);
     if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
if (IDVal == ".frame") {
     // If this is not the end of the statement, report an error.
     if (getLexer().isNot(AsmToken::EndOfStatement)) {
       reportParseError("unexpected token, expected end of statement");
       return false;
     }
 
     getTargetStreamer().emitFrame(StackReg, FrameSizeVal,
                                   ReturnRegOpnd.getGPR32Reg());
+    IsCpRestoreSet = false;
     return false;
   }
 
   if (IDVal == ".set") {
     return parseDirectiveSet();
   }
 
   if (IDVal == ".mask" || IDVal == ".fmask") {

lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
   forbidModuleDirective();
 }
 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
   forbidModuleDirective();
 }
 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
+void MipsTargetStreamer::emitDirectiveCpRestore(
+    SmallVector<MCInst, 3> &StoreInsts, int Offset) {}
 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                                               const MCSymbol &Sym, bool IsReg) {
 }
 void MipsTargetStreamer::emitDirectiveModuleOddSPReg(bool Enabled,
                                                      bool IsO32ABI) {
   if (!Enabled && !IsO32ABI)
     report_fatal_error("+nooddspreg is only valid for O32");
 }

 }
 
 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
   OS << "\t.cpload\t$"
      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
   forbidModuleDirective();
 }
 
+void MipsTargetAsmStreamer::emitDirectiveCpRestore(
+    SmallVector<MCInst, 3> &StoreInsts, int Offset) {
+  OS << "\t.cprestore\t" << Offset << "\n";
+  forbidModuleDirective();
+}
+
 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
                                                  int RegOrOffset,
                                                  const MCSymbol &Sym,
                                                  bool IsReg) {
   OS << "\t.cpsetup\t$"
      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
 
   if (IsReg)
void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
   TmpInst.addOperand(MCOperand::createReg(Mips::GP));
   TmpInst.addOperand(MCOperand::createReg(RegNo));
   getStreamer().EmitInstruction(TmpInst, STI);
 
   forbidModuleDirective();
 }
 
+void MipsTargetELFStreamer::emitDirectiveCpRestore(
+    SmallVector<MCInst, 3> &StoreInsts, int Offset) {
+  // .cprestore offset
+  // When PIC mode is enabled and the O32 ABI is used, this directive expands
+  // to:
+  //    sw $gp, offset($sp)
+  // and adds a corresponding LW after every JAL.
+
+  // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
+  // is used in non-PIC mode.
+  if (!Pic || (getABI().IsN32() || getABI().IsN64()))
+    return;
+
+  for (const MCInst &Inst : StoreInsts)
+    getStreamer().EmitInstruction(Inst, STI);
+
+  forbidModuleDirective();
+}
+
 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
                                                  int RegOrOffset,
                                                  const MCSymbol &Sym,
                                                  bool IsReg) {
   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
     return;
 

lib/Target/Mips/MipsTargetStreamer.h

public:
   virtual void emitDirectiveSetNoDsp();
   virtual void emitDirectiveSetPop();
   virtual void emitDirectiveSetPush();
   virtual void emitDirectiveSetSoftFloat();
   virtual void emitDirectiveSetHardFloat();
 
   // PIC support
   virtual void emitDirectiveCpLoad(unsigned RegNo);
+  virtual void emitDirectiveCpRestore(SmallVector<MCInst, 3> &StoreInsts,
+                                      int Offset);
   virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                                     const MCSymbol &Sym, bool IsReg);
 
   /// Emit a '.module fp=value' directive using the given values.
   /// Updates the .MIPS.abiflags section
   virtual void emitDirectiveModuleFP(MipsABIFlagsSection::FpABIKind Value,
                                      bool Is32BitABI) {
     ABIFlagsSection.setFpABI(Value, Is32BitABI);
public:
   void emitDirectiveSetNoDsp() override;
   void emitDirectiveSetPop() override;
   void emitDirectiveSetPush() override;
   void emitDirectiveSetSoftFloat() override;
   void emitDirectiveSetHardFloat() override;
 
   // PIC support
   void emitDirectiveCpLoad(unsigned RegNo) override;
+  void emitDirectiveCpRestore(SmallVector<MCInst, 3> &StoreInsts,
+                              int Offset) override;
   void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                             const MCSymbol &Sym, bool IsReg) override;
 
   // ABI Flags
   void emitDirectiveModuleFP(MipsABIFlagsSection::FpABIKind Value,
                              bool Is32BitABI) override;
   void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI) override;
   void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override;
public:
   void emitDirectiveInsn() override;
   void emitFrame(unsigned StackReg, unsigned StackSize,
                  unsigned ReturnReg) override;
   void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
   void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
 
   // PIC support
   void emitDirectiveCpLoad(unsigned RegNo) override;
+  void emitDirectiveCpRestore(SmallVector<MCInst, 3> &StoreInsts,
+                              int Offset) override;
   void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                             const MCSymbol &Sym, bool IsReg) override;
 
   // ABI Flags
   void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI) override;
   void emitMipsAbiFlags();
 };
 }
 #endif

test/MC/Mips/cprestore-bad.s

+# RUN: not llvm-mc %s -arch=mips -mcpu=mips32 -relocation-model=pic 2>%t1
+# RUN: FileCheck %s < %t1
+
+  .text
+  .set noreorder
+  .cpload $25
+
+  .set mips16
+  .cprestore 8
+# CHECK: :[[@LINE-1]]:14: error: .cprestore is not supported in Mips16 mode
+  .set nomips16
+
+  .cprestore
+# CHECK: :[[@LINE-1]]:13: error: expected stack offset value
+
+  .cprestore foo
+# CHECK: :[[@LINE-1]]:17: error: stack offset is not an absolute expression
+
+  .cprestore -8
+# CHECK: :[[@LINE-1]]:3: warning: .cprestore with negative stack offset has no effect
+
+  .cprestore 8, 35, bar
+# CHECK: :[[@LINE-1]]:15: error: unexpected token, expected end of statement

test/MC/Mips/cprestore-noreorder.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -relocation-model=pic -show-encoding | \
+# RUN:  FileCheck %s
+
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -relocation-model=pic -filetype=obj -o -| \
+# RUN:  llvm-objdump -d -r -arch=mips - | \
+# RUN:   FileCheck %s -check-prefix=CHECK-FOR-STORE
+
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+micromips -relocation-model=pic -show-encoding | \
+# RUN:  FileCheck %s -check-prefix=MICROMIPS
+
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -relocation-model=static -show-encoding | \
+# RUN:  FileCheck %s -check-prefix=NO-PIC
+
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 -relocation-model=pic -show-encoding | \
+# RUN:  FileCheck %s -check-prefix=BAD-ABI -check-prefix=BAD-ABI-N32
+
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 -relocation-model=pic -show-encoding | \
+# RUN:  FileCheck %s -check-prefix=BAD-ABI -check-prefix=BAD-ABI-N64
+
+  .text
+  .ent foo
+foo:
+  .frame  $sp, 0, $ra
+  .set noreorder
+
+  .cpload $25
+  .cprestore 8
+
+  jal $25
+  jal $4, $25
+  jal foo
+
+  .end foo
+
+# CHECK-FOR-STORE: sw  $gp, 8($sp)
+
+# CHECK: .cprestore 8
+# CHECK: jalr  $25                 # encoding: [0x03,0x20,0xf8,0x09]
+# CHECK: nop                       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lw    $gp, 8($sp)         # encoding: [0x8f,0xbc,0x00,0x08]
+
+# CHECK: jalr  $4,  $25            # encoding: [0x03,0x20,0x20,0x09]
+# CHECK: nop                       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lw    $gp, 8($sp)         # encoding: [0x8f,0xbc,0x00,0x08]
+
+# CHECK: lw    $25, %got(foo)($gp) # encoding: [0x8f,0x99,A,A]
+# CHECK:                           #   fixup A - offset: 0, value: foo@GOT, kind: fixup_Mips_GOT_Local
+# CHECK: addiu $25, $25, %lo(foo)  # encoding: [0x27,0x39,A,A]
+# CHECK:                           #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
+# CHECK: jalr  $25                 # encoding: [0x03,0x20,0xf8,0x09]
+# CHECK: nop                       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lw    $gp, 8($sp)         # encoding: [0x8f,0xbc,0x00,0x08]
+# CHECK: .end  foo
+
+# MICROMIPS: .cprestore 8
+# MICROMIPS: jalrs16 $25                 # encoding: [0x45,0xf9]
+# MICROMIPS: nop                         # encoding: [0x00,0x00,0x00,0x00]
+# MICROMIPS: lw      $gp, 8($sp)         # encoding: [0xff,0x9d,0x00,0x08]
+
+# MICROMIPS: jalrs   $4,  $25            # encoding: [0x00,0x99,0x4f,0x3c]
+# MICROMIPS: nop                         # encoding: [0x00,0x00,0x00,0x00]
+# MICROMIPS: lw      $gp, 8($sp)         # encoding: [0xff,0x9d,0x00,0x08]
+
+# MICROMIPS: lw      $25, %got(foo)($gp) # encoding: [0xff,0x3c,A,A]
+# MICROMIPS:                             #   fixup A - offset: 0, value: foo@GOT, kind: fixup_MICROMIPS_GOT16
+# MICROMIPS: addiu   $25, $25, %lo(foo)  # encoding: [0x33,0x39,A,A]
+# MICROMIPS:                             #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_MICROMIPS_LO16
+# MICROMIPS: jalrs   $ra, $25            # encoding: [0x03,0xf9,0x4f,0x3c]
+# MICROMIPS: nop                         # encoding: [0x0c,0x00]
+# MICROMIPS: lw      $gp, 8($sp)         # encoding: [0xff,0x9d,0x00,0x08]
+# MICROMIPS: .end  foo
+
+# NO-PIC:     .cprestore  8
+# NO-PIC:     jalr  $25         # encoding: [0x03,0x20,0xf8,0x09]
+# NO-PIC-NOT: lw    $gp, 8($sp) # encoding: [0x8f,0xbc,0x00,0x08]
+
+# NO-PIC:     jalr  $4,  $25    # encoding: [0x03,0x20,0x20,0x09]
+# NO-PIC-NOT: lw    $gp, 8($sp) # encoding: [0x8f,0xbc,0x00,0x08]
+
+# NO-PIC:     jal   foo         # encoding: [0b000011AA,A,A,A]
+# NO-PIC:                       #   fixup A - offset: 0, value: foo, kind: fixup_Mips_26
+# NO-PIC-NOT: lw    $gp, 8($sp) # encoding: [0x8f,0xbc,0x00,0x08]
+# NO-PIC:     .end  foo
+
+# BAD-ABI:     .cprestore  8
+# BAD-ABI:     jalr  $25                      # encoding: [0x03,0x20,0xf8,0x09]
+# BAD-ABI-NOT: lw    $gp, 8($sp)              # encoding: [0x8f,0xbc,0x00,0x08]
+
+# BAD-ABI:     jalr  $4,  $25                 # encoding: [0x03,0x20,0x20,0x09]
+# BAD-ABI-NOT: lw    $gp, 8($sp)              # encoding: [0x8f,0xbc,0x00,0x08]
+
+# BAD-ABI-N32: lw    $25, %got_disp(foo)($gp) # encoding: [0x8f,0x99,A,A]
+# BAD-ABI-N64: ld    $25, %got_disp(foo)($gp) # encoding: [0xdf,0x99,A,A]
+# BAD-ABI:                                    #   fixup A - offset: 0, value: foo@GOT_DISP, kind: fixup_Mips_GOT_DISP
+# BAD-ABI:     jalr  $25                      # encoding: [0x03,0x20,0xf8,0x09]
+# BAD-ABI-NOT: lw    $gp, 8($sp)              # encoding: [0x8f,0xbc,0x00,0x08]
+# BAD-ABI:  .end  foo

test/MC/Mips/cprestore-reorder.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -relocation-model=pic -show-encoding | \
+# RUN:  FileCheck %s
+
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -relocation-model=pic -filetype=obj -o -| \
+# RUN:  llvm-objdump -d -r -arch=mips - | \
+# RUN:   FileCheck %s -check-prefix=CHECK-FOR-STORE
+
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+micromips -relocation-model=pic -show-encoding | \
+# RUN:  FileCheck %s -check-prefix=MICROMIPS
+
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -relocation-model=static -show-encoding | \
+# RUN:  FileCheck %s -check-prefix=NO-PIC
+
+# RUN: llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 -relocation-model=pic -show-encoding | \
+# RUN:  FileCheck %s -check-prefix=BAD-ABI -check-prefix=BAD-ABI-N32
+
+# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 -relocation-model=pic -show-encoding | \
+# RUN:  FileCheck %s -check-prefix=BAD-ABI -check-prefix=BAD-ABI-N64
+
+  .text
+  .ent foo
+foo:
+  .frame  $sp, 0, $ra
+  .set noreorder
+  .cpload $25
+  .set reorder
+
+  .cprestore 8
+
+  jal $25
+  jal $4, $25
+  jal foo
+
+  .end foo
+
+# CHECK-FOR-STORE: sw  $gp, 8($sp)
+
+# CHECK: .cprestore 8
+# CHECK: jalr  $25                 # encoding: [0x03,0x20,0xf8,0x09]
+# CHECK: nop                       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lw    $gp, 8($sp)         # encoding: [0x8f,0xbc,0x00,0x08]
+
+# CHECK: jalr  $4,  $25            # encoding: [0x03,0x20,0x20,0x09]
+# CHECK: nop                       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lw    $gp, 8($sp)         # encoding: [0x8f,0xbc,0x00,0x08]
+
+# CHECK: lw    $25, %got(foo)($gp) # encoding: [0x8f,0x99,A,A]
+# CHECK:                           #   fixup A - offset: 0, value: foo@GOT, kind: fixup_Mips_GOT_Local
+# CHECK: addiu $25, $25, %lo(foo)  # encoding: [0x27,0x39,A,A]
+# CHECK:                           #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16
+# CHECK: jalr  $25                 # encoding: [0x03,0x20,0xf8,0x09]
+# CHECK: nop                       # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: lw    $gp, 8($sp)         # encoding: [0x8f,0xbc,0x00,0x08]
+# CHECK: .end  foo
+
+# MICROMIPS: .cprestore 8
+# MICROMIPS: jalrs16 $25                 # encoding: [0x45,0xf9]
+# MICROMIPS: nop                         # encoding: [0x0c,0x00]
+# MICROMIPS: lw      $gp, 8($sp)         # encoding: [0xff,0x9d,0x00,0x08]
+
+# MICROMIPS: jalrs   $4,  $25            # encoding: [0x00,0x99,0x4f,0x3c]
+# MICROMIPS: nop                         # encoding: [0x0c,0x00]
+# MICROMIPS: lw      $gp, 8($sp)         # encoding: [0xff,0x9d,0x00,0x08]
+
+# MICROMIPS: lw      $25, %got(foo)($gp) # encoding: [0xff,0x3c,A,A]
+# MICROMIPS:                             #   fixup A - offset: 0, value: foo@GOT, kind: fixup_MICROMIPS_GOT16
+# MICROMIPS: addiu   $25, $25, %lo(foo)  # encoding: [0x33,0x39,A,A]
+# MICROMIPS:                             #   fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_MICROMIPS_LO16
+# MICROMIPS: jalrs   $ra, $25            # encoding: [0x03,0xf9,0x4f,0x3c]
+# MICROMIPS: nop                         # encoding: [0x0c,0x00]
+# MICROMIPS: lw      $gp, 8($sp)         # encoding: [0xff,0x9d,0x00,0x08]
+# MICROMIPS: .end  foo
+
+# NO-PIC:     .cprestore 8
+# NO-PIC:     jalr  $25         # encoding: [0x03,0x20,0xf8,0x09]
+# NO-PIC-NOT: lw    $gp, 8($sp) # encoding: [0x8f,0xbc,0x00,0x08]
+
+# NO-PIC:     jalr  $4,  $25    # encoding: [0x03,0x20,0x20,0x09]
+# NO-PIC-NOT: lw    $gp, 8($sp) # encoding: [0x8f,0xbc,0x00,0x08]
+
+# NO-PIC:     jal   foo         # encoding: [0b000011AA,A,A,A]
+# NO-PIC:                       #   fixup A - offset: 0, value: foo, kind: fixup_Mips_26
+# NO-PIC-NOT: lw    $gp, 8($sp) # encoding: [0x8f,0xbc,0x00,0x08]
+# NO-PIC:     .end  foo
+
+# BAD-ABI:     .cprestore 8
+# BAD-ABI:     jalr  $25                      # encoding: [0x03,0x20,0xf8,0x09]
+# BAD-ABI-NOT: lw    $gp, 8($sp)              # encoding: [0x8f,0xbc,0x00,0x08]
+
+# BAD-ABI:     jalr  $4,  $25                 # encoding: [0x03,0x20,0x20,0x09]
+# BAD-ABI-NOT: lw    $gp, 8($sp)              # encoding: [0x8f,0xbc,0x00,0x08]
+
+# BAD-ABI-N32: lw    $25, %got_disp(foo)($gp) # encoding: [0x8f,0x99,A,A]
+# BAD-ABI-N64: ld    $25, %got_disp(foo)($gp) # encoding: [0xdf,0x99,A,A]
+# BAD-ABI:                                    #   fixup A - offset: 0, value: foo@GOT_DISP, kind: fixup_Mips_GOT_DISP
+# BAD-ABI:     jalr  $25                      # encoding: [0x03,0x20,0xf8,0x09]
+# BAD-ABI-NOT: lw    $gp, 8($sp)              # encoding: [0x8f,0xbc,0x00,0x08]
+# BAD-ABI:     .end  foo

test/MC/Mips/cprestore-warning-unused.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -relocation-model=pic 2>%t1
+# RUN: FileCheck %s < %t1
+
+  .text
+  .set noreorder
+  .cpload $25
+  .set reorder
+
+  jal $25
+# CHECK: :[[@LINE-1]]:3: warning: no .cprestore used in PIC mode