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Differential D62537

[AMDGPU] Correct the handling of inlineasm output registers.
ClosedPublic

Authored by hliao on May 28 2019, 11:02 AM.

Details

Reviewers
rampitec
alex-t
arsenm
Commits
rG5fc1dfa784dc: [AMDGPU] Correct the handling of inlineasm output registers.
rL361868: [AMDGPU] Correct the handling of inlineasm output registers.
Summary
  • There's a regression due to the cross-block RC assignment. Use the proper way to derive the output register RC in inline asm.

Diff Detail

Repository
rL LLVM

Event Timeline

hliao created this revision.May 28 2019, 11:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 28 2019, 11:02 AM
Herald added subscribers: llvm-commits, hiraditya, eraman and 8 others. · View Herald Transcript
Harbormaster completed remote builds in B32571: Diff 201718.May 28 2019, 11:04 AM
arsenm added inline comments.May 28 2019, 11:08 AM
llvm/test/CodeGen/AMDGPU/inline-asm.ll
289 ↗(On Diff #201718)

Can you not use "r" here?

hliao updated this revision to Diff 201730.May 28 2019, 11:26 AM

revised

Harbormaster completed remote builds in B32579: Diff 201730.May 28 2019, 11:26 AM
hliao marked an inline comment as done.May 28 2019, 11:27 AM
arsenm accepted this revision.May 28 2019, 11:57 AM

LGTM

This revision is now accepted and ready to land.May 28 2019, 11:57 AM
Closed by commit rL361868: [AMDGPU] Correct the handling of inlineasm output registers. (authored by hliao). · Explain WhyMay 28 2019, 12:34 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
3 lines
test/
CodeGen/
AMDGPU/
20 lines

Diff 201742

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 10,238 Lines • ▼ Show 20 Lines if (isa<InlineAsm>(CI->getCalledValue())) {
TargetLowering::AsmOperandInfoVector TargetConstraints = ParseConstraints( TargetLowering::AsmOperandInfoVector TargetConstraints = ParseConstraints(
MF.getDataLayout(), Subtarget->getRegisterInfo(), CS); MF.getDataLayout(), Subtarget->getRegisterInfo(), CS);
for (auto &TC : TargetConstraints) { for (auto &TC : TargetConstraints) {
if (TC.Type == InlineAsm::isOutput) { if (TC.Type == InlineAsm::isOutput) {
ComputeConstraintToUse(TC, SDValue()); ComputeConstraintToUse(TC, SDValue());
unsigned AssignedReg; unsigned AssignedReg;
const TargetRegisterClass *RC; const TargetRegisterClass *RC;
std::tie(AssignedReg, RC) = getRegForInlineAsmConstraint( std::tie(AssignedReg, RC) = getRegForInlineAsmConstraint(
SIRI, TC.ConstraintCode, SIRI, TC.ConstraintCode, TC.ConstraintVT);
getSimpleValueType(MF.getDataLayout(), CS.getType()));
if (RC) { if (RC) {
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg)) if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg))
return true; return true;
else if (SIRI->isSGPRClass(RC)) else if (SIRI->isSGPRClass(RC))
return true; return true;
} }
} }
} }
} }
} }
SetVector<const Value *> Visited; SetVector<const Value *> Visited;
return hasIfBreakUser(V, Visited); return hasIfBreakUser(V, Visited);
} }

llvm/trunk/test/CodeGen/AMDGPU/inline-asm.ll

Show First 20 Lines • Show All 271 Lines • ▼ Show 20 Lines
; of the tablegen default. ; of the tablegen default.
; CHECK-LABEL: {{^}}sgpr96_name_format: ; CHECK-LABEL: {{^}}sgpr96_name_format:
; CHECK: ; sgpr96 s[0:2] ; CHECK: ; sgpr96 s[0:2]
define amdgpu_kernel void @sgpr96_name_format() { define amdgpu_kernel void @sgpr96_name_format() {
entry: entry:
tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1 tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1
ret void ret void
} }
; Check aggregate types are handled properly.
; CHECK-LABEL: mad_u64
; CHECK: v_mad_u64_u32
define void @mad_u64(i32 %x) {
entry:
br i1 undef, label %exit, label %false
false:
%s0 = tail call { i64, i64 } asm sideeffect "v_mad_u64_u32 $0, $1, $2, $3, $4", "=v,=s,v,v,v"(i32 -766435501, i32 %x, i64 0)
br label %exit
exit:
%s1 = phi { i64, i64} [ undef, %entry ], [ %s0, %false]
%v0 = extractvalue { i64, i64 } %s1, 0
%v1 = extractvalue { i64, i64 } %s1, 1
tail call void asm sideeffect "; use $0", "v"(i64 %v0)
tail call void asm sideeffect "; use $0", "v"(i64 %v1)
ret void
}