[X86-64] Fix 256-bit SET0 lowering for non-VLX targets

[greened]

Summary

If we don't have VLX then 256-bit SET0 should be lowered to VPXOR with ZMM registers. This restores functionality accidentally removed by r309926.

[greened]

Oops, needs a testcase. Will add.

[greened]

Added testcase.

[craig.topper]

LGTM

[RKSimon]

@greened This is causing EXPENSIVE_CHECKS buildbot failures - can you fix or shall I revert for now?

$ ":" "RUN: at line 4"
$ "e:\llvm\ninja\bin\llc.exe" "-mtriple=x86_64--" "-mattr=+avx512f" "-o" "-" "E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir"
# command stderr:

# After Instruction Selection
# Machine code for function main: IsSSA, NoPHIs, TracksLiveness, NoVRegs

bb.0.bb0:
  renamable $ymm16 = AVX512_256_SET0
  VMOVAPSZmr $rip, 1, $noreg, @tst_, $noreg, killed renamable $zmm16 :: (store 32 into %ir.lsr.iv1, align 64)
  RET 0

bb.1.bb0:
  %0:vr256 = AVX512_256_SET0
  VMOVAPSYmr $rip, 1, $noreg, @tst_, $noreg, killed %0:vr256 :: (store 32 into %ir.lsr.iv1, align 64)
  RET 0

# End machine code for function main.

*** Bad machine code: Function has NoVRegs property but there are VReg operands ***
- function:    main
LLVM ERROR: Found 1 machine code errors.
Stack dump:
0.      Program arguments: e:\llvm\ninja\bin\llc.exe -mtriple=x86_64-- -mattr=+avx512f -o - E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir
1.      Running pass 'Function Pass Manager' on module 'E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir'.
2.      Running pass 'Verify generated machine code' on function '@main'

[craig.topper]

In D62415#1521084, @RKSimon wrote:

@greened This is causing EXPENSIVE_CHECKS buildbot failures - can you fix or shall I revert for now?

$ ":" "RUN: at line 4"
$ "e:\llvm\ninja\bin\llc.exe" "-mtriple=x86_64--" "-mattr=+avx512f" "-o" "-" "E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir"
# command stderr:

# After Instruction Selection
# Machine code for function main: IsSSA, NoPHIs, TracksLiveness, NoVRegs

bb.0.bb0:
  renamable $ymm16 = AVX512_256_SET0
  VMOVAPSZmr $rip, 1, $noreg, @tst_, $noreg, killed renamable $zmm16 :: (store 32 into %ir.lsr.iv1, align 64)
  RET 0

bb.1.bb0:
  %0:vr256 = AVX512_256_SET0
  VMOVAPSYmr $rip, 1, $noreg, @tst_, $noreg, killed %0:vr256 :: (store 32 into %ir.lsr.iv1, align 64)
  RET 0

# End machine code for function main.

*** Bad machine code: Function has NoVRegs property but there are VReg operands ***
- function:    main
LLVM ERROR: Found 1 machine code errors.
Stack dump:
0.      Program arguments: e:\llvm\ninja\bin\llc.exe -mtriple=x86_64-- -mattr=+avx512f -o - E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir
1.      Running pass 'Function Pass Manager' on module 'E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir'.
2.      Running pass 'Verify generated machine code' on function '@main'

I'm working on a fix for this.

[craig.topper]

In D62415#1521236, @craig.topper wrote:

In D62415#1521084, @RKSimon wrote:

@greened This is causing EXPENSIVE_CHECKS buildbot failures - can you fix or shall I revert for now?

$ ":" "RUN: at line 4"
$ "e:\llvm\ninja\bin\llc.exe" "-mtriple=x86_64--" "-mattr=+avx512f" "-o" "-" "E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir"
# command stderr:

# After Instruction Selection
# Machine code for function main: IsSSA, NoPHIs, TracksLiveness, NoVRegs

bb.0.bb0:
  renamable $ymm16 = AVX512_256_SET0
  VMOVAPSZmr $rip, 1, $noreg, @tst_, $noreg, killed renamable $zmm16 :: (store 32 into %ir.lsr.iv1, align 64)
  RET 0

bb.1.bb0:
  %0:vr256 = AVX512_256_SET0
  VMOVAPSYmr $rip, 1, $noreg, @tst_, $noreg, killed %0:vr256 :: (store 32 into %ir.lsr.iv1, align 64)
  RET 0

# End machine code for function main.

*** Bad machine code: Function has NoVRegs property but there are VReg operands ***
- function:    main
LLVM ERROR: Found 1 machine code errors.
Stack dump:
0.      Program arguments: e:\llvm\ninja\bin\llc.exe -mtriple=x86_64-- -mattr=+avx512f -o - E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir
1.      Running pass 'Function Pass Manager' on module 'E:\llvm\llvm\test\CodeGen\X86\avx512f-256-set0.mir'.
2.      Running pass 'Verify generated machine code' on function '@main'

I'm working on a fix for this.

Should be fixed after r361991

[RKSimon]

In D62415#1521453, @craig.topper wrote:

Should be fixed after r361991

Cheers guys

llvm/lib/Target/X86/X86InstrInfo.cpp

case X86::AVX512_512_SET0: {
     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
       unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
       MIB->getOperand(0).setReg(XReg);
       Expand2AddrUndef(MIB,
                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
       MIB.addReg(SrcReg, RegState::ImplicitDefine);
       return true;
     }
+    if (MI.getOpcode() == X86::AVX512_256_SET0) {
+      // No VLX so we must reference a zmm.
+      unsigned ZReg =
+        TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
+      MIB->getOperand(0).setReg(ZReg);
+    }
     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
   }
   case X86::V_SETALLONES:
     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
   case X86::AVX2_SETALLONES:
     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
   case X86::AVX1_SETALLONES: {
     unsigned Reg = MIB->getOperand(0).getReg();