[RISCV] prefer std::set to std::map

[nickdesaulniers]

Summary

This was flagged in https://www.viva64.com/en/b/0629/ under "Snippet No.
21".

It seems that a std::map is created, but only the keys are ever used.

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< It looks like you meant to use a set >

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Yes we did! Thanks Clippy! (yay!)

[lewis-revill]

Looks like this has already been addressed in D61412!

llvm/utils/TableGen/RISCVCompressInstEmitter.cpp

 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
+#include <set>
 #include <vector>
 using namespace llvm;
 
 #define DEBUG_TYPE "compress-inst-emitter"
 
 namespace {
 class RISCVCompressInstEmitter {
   struct OpData {
void RISCVCompressInstEmitter::evaluateCompressPat(Record *Rec) {
   copy_if(RF, std::back_inserter(PatReqFeatures), [](Record *R) {
     return R->getValueAsBit("AssemblerMatcherPredicate");
   });
 
   CompressPatterns.push_back(CompressPat(SourceInst, DestInst, PatReqFeatures,
                                          SourceOperandMap, DestOperandMap));
 }
 
-static void getReqFeatures(std::map<StringRef, int> &FeaturesMap,
+static void getReqFeatures(std::set<StringRef> &Features,
                            const std::vector<Record *> &ReqFeatures) {
   for (auto &R : ReqFeatures) {
     StringRef AsmCondString = R->getValueAsString("AssemblerCondString");
 
     // AsmCondString has syntax [!]F(,[!]F)*
     SmallVector<StringRef, 4> Ops;
     SplitString(AsmCondString, Ops, ",");
     assert(!Ops.empty() && "AssemblerCondString cannot be empty");
 
     for (auto &Op : Ops) {
       assert(!Op.empty() && "Empty operator");
-      if (FeaturesMap.find(Op) == FeaturesMap.end())
-        FeaturesMap[Op] = FeaturesMap.size();
+      Features.emplace(Op);
     }
   }
 }
 
 unsigned getMCOpPredicate(DenseMap<const Record *, unsigned> &MCOpPredicateMap,
                           std::vector<const Record *> &MCOpPredicates,
                           Record *Rec) {
   unsigned Entry = MCOpPredicateMap[Rec];
for (auto &CompressPat : CompressPatterns) {
     CurOp = Source.TheDef->getName().str();
     // Check current and previous opcode to decide to continue or end a case.
     if (CurOp != PrevOp) {
       if (PrevOp != "")
         CaseStream.indent(6) << "break;\n    } // case " + PrevOp + "\n";
       CaseStream.indent(4) << "case " + Namespace + "::" + CurOp + ": {\n";
     }
 
-    std::map<StringRef, int> FeaturesMap;
+    {
+      std::set<StringRef> Features;
       // Add CompressPat required features.
-    getReqFeatures(FeaturesMap, CompressPat.PatReqFeatures);
+      getReqFeatures(Features, CompressPat.PatReqFeatures);
 
       // Add Dest instruction required features.
       std::vector<Record *> ReqFeatures;
-    std::vector<Record *> RF = Dest.TheDef->getValueAsListOfDefs("Predicates");
+      std::vector<Record *> RF =
+          Dest.TheDef->getValueAsListOfDefs("Predicates");
       copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) {
         return R->getValueAsBit("AssemblerMatcherPredicate");
       });
-    getReqFeatures(FeaturesMap, ReqFeatures);
+      getReqFeatures(Features, ReqFeatures);
 
       // Emit checks for all required features.
-    for (auto &F : FeaturesMap) {
-      StringRef Op = F.first;
+      for (const StringRef &Op : Features) {
         if (Op[0] == '!')
           CondStream.indent(6) << ("!STI.getFeatureBits()[" + Namespace +
                                    "::" + Op.substr(1) + "]")
                                           .str() +
                                       " &&\n";
         else
           CondStream.indent(6)
               << ("STI.getFeatureBits()[" + Namespace + "::" + Op + "]").str() +
                      " &&\n";
       }
+    }
 
     // Start Source Inst operands validation.
     unsigned OpNo = 0;
     for (OpNo = 0; OpNo < Source.Operands.size(); ++OpNo) {
       if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
         if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
           CondStream.indent(6)
               << "(MI.getOperand("