[AArch64] Bit-extract with shifted mask - shr+and (UBFX)

[lebedev.ri]

Summary

I was investigating regressions in https://reviews.llvm.org/D62100#change-c0aDpsCUsZ0a
and it looked like this was the missing piece, but apparently there is something else missing..

Note that i have deleted AArch64TargetLowering::isDesirableToCommuteWithShift()
override, since this adds support for the pattern mentioned there.
And in general that hook is rather useless, since it is forgotten about in *many*
places in DAGCombine, e.g. shl (srl x, c1), c2 fold is not guarded with it.

This highlights a few missing opts:

lsl x8, x8, #3
ldr x0, [x9, x8]

isn't combined into ldr x0, [x9, x8, lsl #3]

lsl w9, w9, #12
lsr w9, w9, #26

should be just

lsr w9, w9, #14

• @no_extract_shrl in rotate-extract.ll means that BFXIL just picks the first opportunity?

[lebedev.ri]

Hmm, this isn't it..
Something much more fine-grained missing.

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
 
   // Transfer memoperands.
   MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(N)->getMemOperand();
   CurDAG->setNodeMemRefs(cast<MachineSDNode>(St), {MemOp});
 
   ReplaceNode(N, St);
 }
 
+static bool isShiftedMask(uint64_t Mask, EVT VT) {
+  assert(VT == MVT::i32 || VT == MVT::i64);
+  if (VT == MVT::i32)
+    return isShiftedMask_32(Mask);
+  return isShiftedMask_64(Mask);
+}
+
+static unsigned countTrailingZeros(uint64_t Val, EVT VT) {
+  assert(VT == MVT::i32 || VT == MVT::i64);
+  if (VT == MVT::i32)
+    return countTrailingZeros<uint32_t>(Val);
+  return countTrailingZeros<uint64_t>(Val);
+}
+
+static unsigned countTrailingOnes(uint64_t Val, EVT VT) {
+  assert(VT == MVT::i32 || VT == MVT::i64);
+  if (VT == MVT::i32)
+    return countTrailingOnes<uint32_t>(Val);
+  return countTrailingOnes<uint64_t>(Val);
+}
+
 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
                                        unsigned &Opc, SDValue &Opd0,
                                        unsigned &LSB, unsigned &MSB,
+                                       unsigned &DstLSB,
                                        unsigned NumberOfIgnoredLowBits,
                                        bool BiggerPattern) {
   assert(N->getOpcode() == ISD::AND &&
          "N must be a AND operation to call this function");
 
   EVT VT = N->getValueType(0);
 
   // Here we can test the type of VT and return false when the type does not
if (!isOpcWithIntImmediate(N, ISD::AND, AndImm))
     return false;
 
   const SDNode *Op0 = N->getOperand(0).getNode();
 
   // Because of simplify-demanded-bits in DAGCombine, the mask may have been
   // simplified. Try to undo that
   AndImm |= maskTrailingOnes<uint64_t>(NumberOfIgnoredLowBits);
 
-  // The immediate is a mask of the low bits iff imm & (imm+1) == 0
-  if (AndImm & (AndImm + 1))
+  // The immediate should be a mask, potentially shifted.
+  if (!isShiftedMask(AndImm, VT))
     return false;
 
   bool ClampMSB = false;
   uint64_t SrlImm = 0;
   // Handle the SRL + ANY_EXTEND case.
   if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
       isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, SrlImm)) {
     // Extend the incoming operand of the SRL to 64-bit.
static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
   // combining/constant folding was performed.
   if (!BiggerPattern && (SrlImm <= 0 || SrlImm >= VT.getSizeInBits())) {
     LLVM_DEBUG(
         (dbgs() << N
                 << ": Found large shift immediate, this should not happen\n"));
     return false;
   }
 
-  LSB = SrlImm;
-  MSB = SrlImm + (VT == MVT::i32 ? countTrailingOnes<uint32_t>(AndImm)
-                                 : countTrailingOnes<uint64_t>(AndImm)) -
-        1;
+  // If the mask is shifted left, then by how much?
+  DstLSB = countTrailingZeros(AndImm, VT);
+  // Pretend that the mask is not shifted so that cto works.
+  AndImm >>= DstLSB;
+
+  // How many bits are we extracting?
+  unsigned NBits = countTrailingOnes(AndImm, VT);
+
+  // Starting from which bit? (accounting for the shifted mask)
+  LSB = SrlImm + DstLSB;
+  // And the last bit to extract is?
+  MSB = LSB + NBits - 1;
+
   if (ClampMSB)
     // Since we're moving the extend before the right shift operation, we need
     // to clamp the MSB to make sure we don't shift in undefined bits instead of
     // the zeros which would get shifted in with the original right shift
     // operation.
     MSB = MSB > 31 ? 31 : MSB;
 
   Opc = VT == MVT::i32 ? AArch64::UBFMWri : AArch64::UBFMXri;
bool AArch64DAGToDAGISel::tryBitfieldExtractOpFromSExt(SDNode *N) {
   SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
                    CurDAG->getTargetConstant(Imms, dl, VT)};
   CurDAG->SelectNodeTo(N, AArch64::SBFMXri, VT, Ops);
   return true;
 }
 
 static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
                                 SDValue &Opd0, unsigned &Immr, unsigned &Imms,
+                                unsigned &DstLSB,
                                 unsigned NumberOfIgnoredLowBits = 0,
                                 bool BiggerPattern = false) {
   if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
     return false;
 
+  DstLSB = 0;
+
   switch (N->getOpcode()) {
   default:
     if (!N->isMachineOpcode())
       return false;
     break;
   case ISD::AND:
-    return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, Immr, Imms,
+    return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, Immr, Imms, DstLSB,
                                       NumberOfIgnoredLowBits, BiggerPattern);
   case ISD::SRL:
   case ISD::SRA:
     return isBitfieldExtractOpFromShr(N, Opc, Opd0, Immr, Imms, BiggerPattern);
 
   case ISD::SIGN_EXTEND_INREG:
     return isBitfieldExtractOpFromSExtInReg(N, Opc, Opd0, Immr, Imms);
   }
case AArch64::UBFMXri:
     Immr = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
     Imms = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
     return true;
   }
   // Unreachable
   return false;
 }
 
+static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount);
+
 bool AArch64DAGToDAGISel::tryBitfieldExtractOp(SDNode *N) {
-  unsigned Opc, Immr, Imms;
+  unsigned Opc, Immr, Imms, DstLSB;
   SDValue Opd0;
-  if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, Immr, Imms))
+  if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, Immr, Imms, DstLSB))
     return false;
 
   EVT VT = N->getValueType(0);
   SDLoc dl(N);
 
-  // If the bit extract operation is 64bit but the original type is 32bit, we
-  // need to add one EXTRACT_SUBREG.
-  if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32) {
-    SDValue Ops64[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, MVT::i64),
-                       CurDAG->getTargetConstant(Imms, dl, MVT::i64)};
+  // In what value type should we perform the extraction?
+  EVT BFMVT = VT;
+  if ((Opc == AArch64::SBFMXri || Opc == AArch64::UBFMXri) && VT == MVT::i32)
+    BFMVT = MVT::i64;
+
+  SDValue BFMOps[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, BFMVT),
+                      CurDAG->getTargetConstant(Imms, dl, BFMVT)};
+  SDNode *BFM = CurDAG->getMachineNode(Opc, dl, BFMVT, BFMOps);
+
+  // If the bit extract operation is 64bit but the original type is 32bit,
+  // we will need to add one EXTRACT_SUBREG.
+  if (BFMVT != VT) {
+    SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, VT);
+    SDValue ExtractOps[] = {SDValue(BFM, 0), SubReg};
+    BFM = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
+                                 ExtractOps);
+  }
+
+  // The extracted bits may be shifted left afterwards.
+  if (DstLSB)
+    BFM = getLeftShift(CurDAG, SDValue(BFM, 0), DstLSB).getNode();
 
-    SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64);
-    SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
-    ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
-                                          MVT::i32, SDValue(BFM, 0), SubReg));
-    return true;
-  }
-
-  SDValue Ops[] = {Opd0, CurDAG->getTargetConstant(Immr, dl, VT),
-                   CurDAG->getTargetConstant(Imms, dl, VT)};
-  CurDAG->SelectNodeTo(N, Opc, VT, Ops);
+  ReplaceNode(N, BFM);
   return true;
 }
 
 /// Does DstMask form a complementary pair with the mask provided by
 /// BitsToBeInserted, suitable for use in a BFI instruction. Roughly speaking,
 /// this asks whether DstMask zeroes precisely those bits that will be set by
 /// the other half.
 static bool isBitfieldDstMask(uint64_t DstMask, const APInt &BitsToBeInserted,
static SDValue getLeftShift(SelectionDAG *CurDAG, SDValue Op, int ShlAmount) {
   }
 
   return SDValue(ShiftNode, 0);
 }
 
 /// Does this tree qualify as an attempt to move a bitfield into position,
 /// essentially "(and (shl VAL, N), Mask)".
 static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
-                                    bool BiggerPattern,
-                                    SDValue &Src, int &ShiftAmount,
-                                    int &MaskWidth) {
+                                    bool BiggerPattern, SDValue &Src,
+                                    unsigned &ShiftAmount,
+                                    unsigned &MaskWidth) {
   EVT VT = Op.getValueType();
   unsigned BitWidth = VT.getSizeInBits();
   (void)BitWidth;
   assert(BitWidth == 32 || BitWidth == 64);
 
   KnownBits Known = CurDAG->computeKnownBits(Op);
 
   // Non-zero in the sense that they're not provably zero, which is the key
static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
   // which case it is not profitable to insert an extra shift.
   if (ShlImm - ShiftAmount != 0 && !BiggerPattern)
     return false;
   Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
 
   return true;
 }
 
-static bool isShiftedMask(uint64_t Mask, EVT VT) {
-  assert(VT == MVT::i32 || VT == MVT::i64);
-  if (VT == MVT::i32)
-    return isShiftedMask_32(Mask);
-  return isShiftedMask_64(Mask);
-}
-
 // Generate a BFI/BFXIL from 'or (and X, MaskImm), OrImm' iff the value being
 // inserted only sets known zero bits.
 static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
   assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
 
   EVT VT = N->getValueType(0);
   if (VT != MVT::i32 && VT != MVT::i64)
     return false;
for (int I = 0; I < 4; ++I) {
     unsigned ImmR, ImmS;
     bool BiggerPattern = I / 2;
     SDValue OrOpd0Val = N->getOperand(I % 2);
     SDNode *OrOpd0 = OrOpd0Val.getNode();
     SDValue OrOpd1Val = N->getOperand((I + 1) % 2);
     SDNode *OrOpd1 = OrOpd1Val.getNode();
 
     unsigned BFXOpc;
-    int DstLSB, Width;
-    if (isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Src, ImmR, ImmS,
+    unsigned DstLSB, Width;
+    if (isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Src, ImmR, ImmS, DstLSB,
                             NumberOfIgnoredLowBits, BiggerPattern)) {
+      if (DstLSB != 0)
+        continue; // BFXIL inserts starting with bit 0, always.
       // Check that the returned opcode is compatible with the pattern,
       // i.e., same type and zero extended (U and not S)
       if ((BFXOpc != AArch64::UBFMXri && VT == MVT::i64) ||
           (BFXOpc != AArch64::UBFMWri && VT == MVT::i32))
         continue;
 
       // Compute the width of the bitfield insertion
-      DstLSB = 0;
       Width = ImmS - ImmR + 1;
       // FIXME: This constraint is to catch bitfield insertion we may
       // want to widen the pattern if we want to grab general bitfied
       // move case
       if (Width <= 0)
         continue;
 
       // If the mask on the insertee is correct, we have a BFXIL operation. We
       // can share the ImmR and ImmS values from the already-computed UBFM.
-    } else if (isBitfieldPositioningOp(CurDAG, OrOpd0Val,
-                                       BiggerPattern,
-                                       Src, DstLSB, Width)) {
+    } else if (isBitfieldPositioningOp(CurDAG, OrOpd0Val, BiggerPattern, Src,
+                                       DstLSB, Width)) {
       ImmR = (BitWidth - DstLSB) % BitWidth;
       ImmS = Width - 1;
     } else
       continue;
 
     // Check the second part of the pattern
     EVT VT = OrOpd1Val.getValueType();
     assert((VT == MVT::i32 || VT == MVT::i64) && "unexpected OR operand");
bool AArch64DAGToDAGISel::tryBitfieldInsertInZeroOp(SDNode *N) {
   if (N->getOpcode() != ISD::AND)
     return false;
 
   EVT VT = N->getValueType(0);
   if (VT != MVT::i32 && VT != MVT::i64)
     return false;
 
   SDValue Op0;
-  int DstLSB, Width;
+  unsigned DstLSB, Width;
   if (!isBitfieldPositioningOp(CurDAG, SDValue(N, 0), /*BiggerPattern=*/false,
                                Op0, DstLSB, Width))
     return false;
 
   // ImmR is the rotate right amount.
   unsigned ImmR = (VT.getSizeInBits() - DstLSB) % VT.getSizeInBits();
   // ImmS is the most significant bit of the source to be moved.
   unsigned ImmS = Width - 1;

lib/Target/AArch64/AArch64ISelLowering.h

public:
 
   /// Return true if an FMA operation is faster than a pair of fmul and fadd
   /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
   /// returns true, otherwise fmuladd is expanded to fmul + fadd.
   bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
 
   const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
 
-  /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
-  bool isDesirableToCommuteWithShift(const SDNode *N,
-                                     CombineLevel Level) const override;
-
   /// Returns true if it is beneficial to convert a load of a constant
   /// to just the constant itself.
   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                          Type *Ty) const override;
 
   /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
   /// with this index.
   bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,

lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
   // site. Hence we include LR in the scratch registers, which are in turn added
   // as implicit-defs for stackmaps and patchpoints.
   static const MCPhysReg ScratchRegs[] = {
     AArch64::X16, AArch64::X17, AArch64::LR, 0
   };
   return ScratchRegs;
 }
 
-bool
-AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N,
-                                                     CombineLevel Level) const {
-  N = N->getOperand(0).getNode();
-  EVT VT = N->getValueType(0);
-    // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
-    // it with shift to let it be lowered to UBFX.
-  if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
-      isa<ConstantSDNode>(N->getOperand(1))) {
-    uint64_t TruncMask = N->getConstantOperandVal(1);
-    if (isMask_64(TruncMask) &&
-      N->getOperand(0).getOpcode() == ISD::SRL &&
-      isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
-      return false;
-  }
-  return true;
-}
-
 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                               Type *Ty) const {
   assert(Ty->isIntegerTy());
 
   unsigned BitSize = Ty->getPrimitiveSizeInBits();
   if (BitSize == 0)
     return false;
 

test/CodeGen/AArch64/arm64-bitfield-extract.ll

end:
   ret i80 %conv3
 }
 
 ; Check if we can still catch UBFX when "AND" is used by SHL.
 @arr = external global [8 x [64 x i64]]
 define i64 @fct21(i64 %x) {
 ; LLC-LABEL: fct21:
 ; LLC:       // %bb.0: // %entry
-; LLC-NEXT:    adrp x9, arr
 ; LLC-NEXT:    ubfx x8, x0, #4, #4
+; LLC-NEXT:    adrp x9, arr
+; LLC-NEXT:    lsl x8, x8, #3
 ; LLC-NEXT:    add x9, x9, :lo12:arr
-; LLC-NEXT:    ldr x0, [x9, x8, lsl #3]
+; LLC-NEXT:    ldr x0, [x9, x8]
 ; LLC-NEXT:    ret
 ; OPT-LABEL: @fct21(
 ; OPT-NEXT:  entry:
 ; OPT-NEXT:    [[SHR:%.*]] = lshr i64 [[X:%.*]], 4
 ; OPT-NEXT:    [[AND:%.*]] = and i64 [[SHR]], 15
 ; OPT-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [8 x [64 x i64]], [8 x [64 x i64]]* @arr, i64 0, i64 0, i64 [[AND]]
 ; OPT-NEXT:    [[TMP0:%.*]] = load i64, i64* [[ARRAYIDX]], align 8
 ; OPT-NEXT:    ret i64 [[TMP0]]

test/CodeGen/AArch64/bitfield-insert.ll

 
 ; Bitfield insert where there's a left-over shr needed at the beginning
 ; (e.g. result of str.bf1 = str.bf2)
 define void @test_32bit_with_shr(i32* %existing, i32* %new) {
 ; CHECK-LABEL: test_32bit_with_shr:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr w8, [x0]
 ; CHECK-NEXT:    ldr w9, [x1]
-; CHECK-NEXT:    lsr w9, w9, #14
+; CHECK-NEXT:    lsl w9, w9, #12
+; CHECK-NEXT:    lsr w9, w9, #26
 ; CHECK-NEXT:    bfi w8, w9, #26, #5
 ; CHECK-NEXT:    str w8, [x0]
 ; CHECK-NEXT:    ret
   %oldval = load volatile i32, i32* %existing
   %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
 
   %newval = load i32, i32* %new
   %newval_shifted = shl i32 %newval, 12

test/CodeGen/AArch64/extract-bits.ll

; CHECK-NEXT:    ret
   %tmp1 = and i32 %tmp0, 1023
   ret i32 %tmp1
 }
 
 ; Should be still fine, but the mask is shifted
 define i32 @c1_i32(i32 %arg) nounwind {
 ; CHECK-LABEL: c1_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #19
-; CHECK-NEXT:    and w0, w8, #0xffc
+; CHECK-NEXT:    ubfx w8, w0, #21, #10
+; CHECK-NEXT:    lsl w0, w8, #2
 ; CHECK-NEXT:    ret
   %tmp0 = lshr i32 %arg, 19
   %tmp1 = and i32 %tmp0, 4092
   ret i32 %tmp1
 }
 
 ; Should be still fine, but the result is shifted left afterwards
 define i32 @c2_i32(i32 %arg) nounwind {
 ; CHECK-LABEL: c2_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ubfx w8, w0, #19, #10
 ; CHECK-NEXT:    lsl w0, w8, #2
 ; CHECK-NEXT:    ret
   %tmp0 = lshr i32 %arg, 19
   %tmp1 = and i32 %tmp0, 1023
   %tmp2 = shl i32 %tmp1, 2
   ret i32 %tmp2
 }
 
 ; The mask covers newly shifted-in bit
 define i32 @c4_i32_bad(i32 %arg) nounwind {
 ; CHECK-LABEL: c4_i32_bad:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #19
-; CHECK-NEXT:    and w0, w8, #0x1ffe
+; CHECK-NEXT:    lsr w8, w0, #20
+; CHECK-NEXT:    lsl w0, w8, #1
 ; CHECK-NEXT:    ret
   %tmp0 = lshr i32 %arg, 19
   %tmp1 = and i32 %tmp0, 16382
   ret i32 %tmp1
 }
 
 ; i64
 
 ; The most canonical variant
 define i64 @c0_i64(i64 %arg) nounwind {
 ; CHECK-LABEL: c0_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ubfx x0, x0, #51, #10
 ; CHECK-NEXT:    ret
   %tmp0 = lshr i64 %arg, 51
   %tmp1 = and i64 %tmp0, 1023
   ret i64 %tmp1
 }
 
 ; Should be still fine, but the mask is shifted
 define i64 @c1_i64(i64 %arg) nounwind {
 ; CHECK-LABEL: c1_i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr x8, x0, #51
-; CHECK-NEXT:    and x0, x8, #0xffc
+; CHECK-NEXT:    ubfx x8, x0, #53, #10
+; CHECK-NEXT:    lsl x0, x8, #2
 ; CHECK-NEXT:    ret
   %tmp0 = lshr i64 %arg, 51
   %tmp1 = and i64 %tmp0, 4092
   ret i64 %tmp1
 }
 
 ; Should be still fine, but the result is shifted left afterwards
 define i64 @c2_i64(i64 %arg) nounwind {
 ; CHECK-LABEL: c2_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ubfx x8, x0, #51, #10
 ; CHECK-NEXT:    lsl x0, x8, #2
 ; CHECK-NEXT:    ret
   %tmp0 = lshr i64 %arg, 51
   %tmp1 = and i64 %tmp0, 1023
   %tmp2 = shl i64 %tmp1, 2
   ret i64 %tmp2
 }
 
 ; The mask covers newly shifted-in bit
 define i64 @c4_i64_bad(i64 %arg) nounwind {
 ; CHECK-LABEL: c4_i64_bad:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr x8, x0, #51
-; CHECK-NEXT:    and x0, x8, #0x1ffe
+; CHECK-NEXT:    lsr x8, x0, #52
+; CHECK-NEXT:    lsl x0, x8, #1
 ; CHECK-NEXT:    ret
   %tmp0 = lshr i64 %arg, 51
   %tmp1 = and i64 %tmp0, 16382
   ret i64 %tmp1
 }
 
 ; ---------------------------------------------------------------------------- ;
 ; Constant, storing the result afterwards.

test/CodeGen/AArch64/pull-binop-through-shift.ll

; CHECK-NEXT:    ret
   ret i32 %r
 }
 
 ; logical shift right
 
 define i32 @and_signbit_lshr(i32 %x, i32* %dst) {
 ; CHECK-LABEL: and_signbit_lshr:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #8
-; CHECK-NEXT:    and w0, w8, #0xffff00
+; CHECK-NEXT:    lsr w8, w0, #16
+; CHECK-NEXT:    lsl w0, w8, #8
 ; CHECK-NEXT:    str w0, [x1]
 ; CHECK-NEXT:    ret
   %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
   %r = lshr i32 %t0, 8
   store i32 %r, i32* %dst
   ret i32 %r
 }
 define i32 @and_nosignbit_lshr(i32 %x, i32* %dst) {
 ; CHECK-LABEL: and_nosignbit_lshr:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #8
-; CHECK-NEXT:    and w0, w8, #0x7fff00
+; CHECK-NEXT:    ubfx w8, w0, #16, #15
+; CHECK-NEXT:    lsl w0, w8, #8
 ; CHECK-NEXT:    str w0, [x1]
 ; CHECK-NEXT:    ret
   %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
   %r = lshr i32 %t0, 8
   store i32 %r, i32* %dst
   ret i32 %r
 }
 
; CHECK-NEXT:    ret
   %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
   %r = ashr i32 %t0, 8
   store i32 %r, i32* %dst
   ret i32 %r
 }
 define i32 @and_nosignbit_ashr(i32 %x, i32* %dst) {
 ; CHECK-LABEL: and_nosignbit_ashr:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #8
-; CHECK-NEXT:    and w0, w8, #0x7fff00
+; CHECK-NEXT:    ubfx w8, w0, #16, #15
+; CHECK-NEXT:    lsl w0, w8, #8
 ; CHECK-NEXT:    str w0, [x1]
 ; CHECK-NEXT:    ret
   %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
   %r = ashr i32 %t0, 8
   store i32 %r, i32* %dst
   ret i32 %r
 }
 

test/CodeGen/AArch64/rotate-extract.ll

; CHECK-NEXT:    ret
   %out = or i64 %lhs_shift, %rhs_mul
   ret i64 %out
 }
 
 ; Result would overshift
 define i32 @no_extract_shrl(i32 %i) nounwind {
 ; CHECK-LABEL: no_extract_shrl:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #3
-; CHECK-NEXT:    lsr w0, w0, #9
-; CHECK-NEXT:    bfi w0, w8, #28, #4
+; CHECK-NEXT:    lsl w8, w0, #25
+; CHECK-NEXT:    and w8, w8, #0xf0000000
+; CHECK-NEXT:    bfxil w8, w0, #9, #23
+; CHECK-NEXT:    mov w0, w8
 ; CHECK-NEXT:    ret
   %lhs_div = lshr i32 %i, 3
   %rhs_div = lshr i32 %i, 9
   %lhs_shift = shl i32 %lhs_div, 28
   %out = or i32 %lhs_shift, %rhs_div
   ret i32 %out
 }
 

test/CodeGen/AArch64/selectcc-to-shiftand.ll

; CHECK-NEXT:    ret
   ret i32 %retval
 }
 
 ; Compare if negative and select of constants where one constant is zero and the other is a single bit.
 
 define i32 @neg_sel_special_constant(i32 %a) {
 ; CHECK-LABEL: neg_sel_special_constant:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #22
-; CHECK-NEXT:    and w0, w8, #0x200
+; CHECK-NEXT:    lsr w8, w0, #31
+; CHECK-NEXT:    lsl w0, w8, #9
 ; CHECK-NEXT:    ret
   %tmp.1 = icmp slt i32 %a, 0
   %retval = select i1 %tmp.1, i32 512, i32 0
   ret i32 %retval
 }
 
 ; Compare if negative and select variable or zero.