[AMDGPU][MC] Enabled labels as operands of s_call_b64 and s_cbranch_i_fork

[dp]

Summary

See bug 41888: https://bugs.llvm.org/show_bug.cgi?id=41888

Should we also rename all *sopp* helpers like getSOPPBrEncoding to be *sop*? This will affect many lines of code so I'm not sure.

[artem.tamazov]

What would occur if offset exceeds int16 due to destination label is too far?

[dp]

This is checked during fixups relaxations. An error is reported if the offset does not fit in 16 bits. See lit test max-branch-distance.s

[artem.tamazov]

Great, thanks!

llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td

let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0",
     Constraints = "$sdst = $src0" in {
   def S_ADDK_I32 : SOPK_32TIE <"s_addk_i32">;
   def S_MULK_I32 : SOPK_32TIE <"s_mulk_i32">;
 }
 
 let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in
 def S_CBRANCH_I_FORK : SOPK_Pseudo <
   "s_cbranch_i_fork",
-  (outs), (ins SReg_64:$sdst, s16imm:$simm16),
+  (outs), (ins SReg_64:$sdst, sopp_brtarget:$simm16),
   "$sdst, $simm16"
 >;
 
 let mayLoad = 1 in {
 def S_GETREG_B32 : SOPK_Pseudo <
   "s_getreg_b32",
   (outs SReg_32:$sdst), (ins hwreg:$simm16),
   "$sdst, $simm16"
class SOPK_WAITCNT<string opName, list<dag> pat=[]> :
   let mayStore = 1;
   let has_sdst = 1; // First source takes place of sdst in encoding
 }
 
 let SubtargetPredicate = isGFX9Plus in {
   def S_CALL_B64 : SOPK_Pseudo<
       "s_call_b64",
       (outs SReg_64:$sdst),
-      (ins s16imm:$simm16),
+      (ins sopp_brtarget:$simm16),
       "$sdst, $simm16"> {
     let isCall = 1;
   }
 } // End SubtargetPredicate = isGFX9Plus
 
 let SubtargetPredicate = isGFX10Plus in {
   def S_VERSION : SOPK_Pseudo<
       "s_version",

llvm/trunk/test/MC/AMDGPU/labels-branch-gfx9.s

+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -filetype=obj %s | llvm-objdump -disassemble -mcpu=gfx900 - | FileCheck %s --check-prefix=BIN
+
+loop_start:
+
+s_call_b64 s[10:11], loop_end
+// GFX9: s_call_b64 s[10:11], loop_end   ; encoding: [A,A,0x8a,0xba]
+// GFX9-NEXT: ;   fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
+// BIN: loop_start:
+// BIN-NEXT: s_call_b64 s[10:11], loop_end // 000000000000: BA8A0001
+
+s_call_b64 s[10:11], loop_start
+// GFX9: s_call_b64 s[10:11], loop_start ; encoding: [A,A,0x8a,0xba]
+// GFX9-NEXT: ;   fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
+// BIN: s_call_b64 s[10:11], loop_start  // 000000000004: BA8AFFFE
+// BIN: loop_end:
+
+loop_end:
+  s_nop 0

llvm/trunk/test/MC/AMDGPU/sopk.s

 // SICI: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]
 // VI9:  s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb7]
 
 s_mulk_i32 s2, 0xFFFF
 // SICI: s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x02,0xb8]
 // VI9:  s_mulk_i32 s2, 0xffff ; encoding: [0xff,0xff,0x82,0xb7]
 
 s_cbranch_i_fork s[2:3], 0x6
-// SICI: s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
-// VI9:  s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
+// SICI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x82,0xb8]
+// VI9:  s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
 
 // raw number mapped to known HW register
 s_getreg_b32 s2, 0x6
 // SICI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x02,0xb9]
 // VI9:  s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1) ; encoding: [0x06,0x00,0x82,0xb8]
 
 // HW register identifier, non-default offset/width
 s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31)

 // SICI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x80,0xba,0xff,0x00,0x00,0x00]
 // VI9:  s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
 
 s_endpgm_ordered_ps_done
 // GFX9:     s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
 // NOSICIVI: error: instruction not supported on this GPU
 
 s_call_b64 s[12:13], 12609
-// GFX9:     s_call_b64 s[12:13], 0x3141 ; encoding: [0x41,0x31,0x8c,0xba]
+// GFX9:     s_call_b64 s[12:13], 12609 ; encoding: [0x41,0x31,0x8c,0xba]
 // NOSICIVI: error: instruction not supported on this GPU
 
 s_call_b64 s[100:101], 12609
-// GFX9:     s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
+// GFX9:     s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0xe4,0xba]
 // NOSICIVI: error: instruction not supported on this GPU
 
 s_call_b64 s[10:11], 49617
-// GFX9:     s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
+// GFX9:     s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x8a,0xba]
 // NOSICIVI: error: instruction not supported on this GPU

llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_gfx9.txt

 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
 
 # GFX9: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0x9e,0xbf]
 0x00,0x00,0x9e,0xbf
 
-# GFX9: s_call_b64 s[10:11], 0x3141 ; encoding: [0x41,0x31,0x8a,0xba]
+# GFX9: s_call_b64 s[10:11], 12609 ; encoding: [0x41,0x31,0x8a,0xba]
 0x41,0x31,0x8a,0xba
 
-# GFX9: s_call_b64 s[100:101], 0x3141 ; encoding: [0x41,0x31,0xe4,0xba]
+# GFX9: s_call_b64 s[100:101], 12609 ; encoding: [0x41,0x31,0xe4,0xba]
 0x41,0x31,0xe4,0xba
 
-# GFX9: s_call_b64 s[10:11], 0xc1d1 ; encoding: [0xd1,0xc1,0x8a,0xba]
+# GFX9: s_call_b64 s[10:11], 49617 ; encoding: [0xd1,0xc1,0x8a,0xba]
 0xd1,0xc1,0x8a,0xba

llvm/trunk/test/MC/Disassembler/AMDGPU/sopk_vi.txt

 0x06 0x00 0x82 0xb6
 
 # VI:   s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]
 0x06 0x00 0x02 0xb7
 
 # VI:   s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
 0x06 0x00 0x82 0xb7
 
-# VI:   s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
+# VI:   s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
 0x06 0x00 0x02 0xb8
 
 # VI:   s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x82,0xb8]
 0x06 0xf8 0x82 0xb8
 
 # VI:   s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]
 0x33,0xf8,0x82,0xb8
 
 # VI:   s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
 0x73,0xf0,0x82,0xb8
 
 # VI:   s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]
 0x06 0x00 0x02 0xb9
 
 # VI:   s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
 0x45 0xf0 0x00 0xba 0xff 0x00 0x00 0x00