[Mips] LLVM and GAS now use same instructions for CFA Definition. NFCI

[mbrkusanin]

Summary

LLVM previously used DW_CFA_def_cfa instruction in .eh_frame to set the register
and offset for current CFA rule. We change it to DW_CFA_def_cfa_register which
is the same one used by GAS that only changes the register but keeping the old
offset.

[mbrkusanin]

It seems that using the instruction without offset does not affect exception
handling. Testing it on a couple of simple examples where unwinding the stack
is necessary gives correct output. This is expected since GAS uses the same
instructions. Documentation does not indicate that there are any differences
between these two instructions if we don't change the offset (in code before the
patch value passed was +0). This patch may be unnecessary but if we want to be
sure that there aren't any unexpected problems down the line we could apply it.

Now in .eh_frame instead of:

DW_CFA_def_cfa: reg29 +0

we have:

DW_CFA_def_cfa_register: reg29
DW_CFA_nop:

DW_CFA_nop is used for padding since DW_CFA_def_cfa_register is shorter (has one
less operand).

[atanasyan]

LGTM

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
   return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
 }
 
 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
                                       const Triple &TT) {
   MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
 
   unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
-  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
+  MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP);
   MAI->addInitialFrameState(Inst);
 
   return MAI;
 }
 
 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
                                               unsigned SyntaxVariant,
                                               const MCAsmInfo &MAI,

llvm/trunk/test/MC/Mips/cfi-advance-loc.s

 // CHECK-LE-NEXT:   Offset: 0x10180
 // CHECK-LE-NEXT:   Size: 68
 // CHECK-LE-NEXT:   Link: 0
 // CHECK-LE-NEXT:   Info: 0
 // CHECK-LE-NEXT:   AddressAlignment: 4
 // CHECK-LE-NEXT:   EntrySize: 0
 // CHECK-LE-NEXT:   SectionData (
 // CHECK-LE-NEXT:     0000: 10000000 00000000 017A5200 017C1F01
-// CHECK-LE-NEXT:     0010: 0B0C1D00 14000000 18000000 00000000
+// CHECK-LE-NEXT:     0010: 0B0D1D00 14000000 18000000 00000000
 // CHECK-LE-NEXT:     0020: 04010000 00030001 0E080000 14000000
 // CHECK-LE-NEXT:     0030: 30000000 04010000 04000100 00040000
 // CHECK-LE-NEXT:     0040: 01000E08
 // CHECK-LE-NEXT:   )
 // CHECK-LE-NEXT: }
 
 // CHECK-BE:      Section {
 // CHECK-BE:        Index: 7
 // CHECK-BE:        Name: .eh_frame (44)
 // CHECK-BE-NEXT:   Type: SHT_PROGBITS (0x1)
 // CHECK-BE-NEXT:   Flags [ (0x2)
 // CHECK-BE-NEXT:     SHF_ALLOC (0x2)
 // CHECK-BE-NEXT:   ]
 // CHECK-BE-NEXT:   Address: 0x0
 // CHECK-BE-NEXT:   Offset: 0x10180
 // CHECK-BE-NEXT:   Size: 68
 // CHECK-BE-NEXT:   Link: 0
 // CHECK-BE-NEXT:   Info: 0
 // CHECK-BE-NEXT:   AddressAlignment: 4
 // CHECK-BE-NEXT:   EntrySize: 0
 // CHECK-BE-NEXT:   SectionData (
 // CHECK-BE-NEXT:     0000: 00000010 00000000 017A5200 017C1F01
-// CHECK-BE-NEXT:     0010: 0B0C1D00 00000014 00000018 00000000
+// CHECK-BE-NEXT:     0010: 0B0D1D00 00000014 00000018 00000000
 // CHECK-BE-NEXT:     0020: 00000104 00030100 0E080000 00000014
 // CHECK-BE-NEXT:     0030: 00000030 00000104 00010004 00040001
 // CHECK-BE-NEXT:     0040: 00000E08
 // CHECK-BE-NEXT:   )
 // CHECK-BE-NEXT: }

llvm/trunk/test/MC/Mips/cfi-encoding.s

 # RUN: llvm-mc -filetype=obj -triple mips--gnu -g %s \
 # RUN:   | llvm-objdump -s -section=.eh_frame - | FileCheck --check-prefix=O32 %s
 # RUN: llvm-mc -filetype=obj -triple mips64--gnuabin32 -g %s \
 # RUN:   | llvm-objdump -s -section=.eh_frame - | FileCheck --check-prefix=N32 %s
 # RUN: llvm-mc -filetype=obj -triple mips64--gnuabi64 -g %s \
 # RUN:   | llvm-objdump -s -section=.eh_frame - | FileCheck --check-prefix=N64 %s
 
 # O32: 0000 00000010 00000000 017a5200 017c1f01
-# O32: 0010 0b0c1d00 00000010 00000018 00000000
+# O32: 0010 0b0d1d00 00000010 00000018 00000000
 # O32: 0020 00000004 00000000
 
 # N32: 0000 00000010 00000000 017a5200 017c1f01
-# N32: 0010 0b0c1d00 00000010 00000018 00000000
+# N32: 0010 0b0d1d00 00000010 00000018 00000000
 # N32: 0020 00000004 00000000
 
 # N64: 0000 00000010 00000000 017a5200 01781f01
-# N64: 0010 0c0c1d00 00000018 00000018 00000000
+# N64: 0010 0c0d1d00 00000018 00000018 00000000
 # N64: 0020 00000000 00000000 00000004 00000000
 
 foo:
   .cfi_startproc
   nop
   .cfi_endproc

llvm/trunk/test/MC/Mips/eh-frame.s

 // DWARF32: 00000000 00000010 ffffffff CIE
 // DWARF32:   Version:               1
 // DWARF32:   Augmentation:          "zR"
 // DWARF32:   Code alignment factor: 1
 // DWARF32:   Data alignment factor: -4
 // DWARF32:   Return address column: 31
 // DWARF32:   Augmentation data:     0B
 //                                   ^^ fde pointer encoding: DW_EH_PE_sdata4
-// DWARF32:   DW_CFA_def_cfa: reg29 +0
-// FIXME: The instructions are different from the ones produces by gas.
+// DWARF32:   DW_CFA_def_cfa_register: reg29
 //
 // DWARF32: 00000014 00000010 00000018 FDE cie=00000018 pc=00000000...00000000
 // DWARF32:   DW_CFA_nop:
 // DWARF32:   DW_CFA_nop:
 // DWARF32:   DW_CFA_nop:
 
 // DWARF64: 00000000 00000010 ffffffff CIE
 // DWARF64:   Version:               1
 // DWARF64:   Augmentation:          "zR"
 // DWARF64:   Code alignment factor: 1
 // DWARF64:   Data alignment factor: -8
 //                                   ^^ GAS uses -4. Should be ok as long as
 //                                      all offsets we need are a multiple of 8.
 // DWARF64:   Return address column: 31
 // DWARF64:   Augmentation data:     0C
 //                                   ^^ fde pointer encoding: DW_EH_PE_sdata8
-// DWARF64:   DW_CFA_def_cfa: reg29 +0
-// FIXME: The instructions are different from the ones produces by gas.
+// DWARF64:   DW_CFA_def_cfa_register: reg29
 //
 // DWARF64: 00000014 00000018 00000018 FDE cie=00000018 pc=00000000...00000000
 // DWARF64:   DW_CFA_nop:
 // DWARF64:   DW_CFA_nop:
 // DWARF64:   DW_CFA_nop: