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Differential D61704

[AMDGPU] gfx1010 changes for PAL metadata
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Authored by rampitec on May 8 2019, 3:54 PM.

Details

Reviewers
kzhuravl
msearles
Commits
rZORGe9377c93cf46: [AMDGPU] gfx1010 changes for PAL metadata
rZORG241d79de037d: [AMDGPU] gfx1010 changes for PAL metadata
rGe9377c93cf46: [AMDGPU] gfx1010 changes for PAL metadata
rG241d79de037d: [AMDGPU] gfx1010 changes for PAL metadata
rG4d4c9e0757c9: [AMDGPU] gfx1010 changes for PAL metadata
rL360353: [AMDGPU] gfx1010 changes for PAL metadata

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Event Timeline

rampitec created this revision.May 8 2019, 3:54 PM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptMay 8 2019, 3:54 PM
kzhuravl accepted this revision.May 9 2019, 8:44 AM

LGTM

This revision is now accepted and ready to land.May 9 2019, 8:44 AM
Closed by commit rL360353: [AMDGPU] gfx1010 changes for PAL metadata (authored by rampitec). · Explain WhyMay 9 2019, 9:32 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptMay 9 2019, 9:32 AM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
Utils/
5 lines

Diff 198738

lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp

Show First 20 Lines • Show All 246 Lines • ▼ Show 20 Lines const char *Name;
{PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"}, {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS, "SPI_SHADER_PGM_RSRC1_LS"},
{PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"}, {PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1, "SPI_SHADER_PGM_RSRC2_LS"},
{PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"}, {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS, "SPI_SHADER_PGM_RSRC1_HS"},
{PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"}, {PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1, "SPI_SHADER_PGM_RSRC2_HS"},
{PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"}, {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES, "SPI_SHADER_PGM_RSRC1_ES"},
{PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"}, {PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
{PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"}, {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
{PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"}, {PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
{PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"},
{PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"}, {PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
{PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"}, {PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
{PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"}, {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
{PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"}, {PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
{PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"}, {PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
{PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"}, {PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
{PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"},
{PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"},
// Registers not known to code generation. // Registers not known to code generation.
{0x2c07, "SPI_SHADER_PGM_RSRC3_PS"}, {0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
{0x2c46, "SPI_SHADER_PGM_RSRC3_VS"}, {0x2c46, "SPI_SHADER_PGM_RSRC3_VS"},
{0x2c87, "SPI_SHADER_PGM_RSRC3_GS"}, {0x2c87, "SPI_SHADER_PGM_RSRC3_GS"},
{0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"}, {0x2cc7, "SPI_SHADER_PGM_RSRC3_ES"},
{0x2d07, "SPI_SHADER_PGM_RSRC3_HS"}, {0x2d07, "SPI_SHADER_PGM_RSRC3_HS"},
{0x2d47, "SPI_SHADER_PGM_RSRC3_LS"}, {0x2d47, "SPI_SHADER_PGM_RSRC3_LS"},
Show All 9 Lines const char *Name;
{0x2c81, "SPI_SHADER_PGM_RSRC4_GS"}, {0x2c81, "SPI_SHADER_PGM_RSRC4_GS"},
{0x2e18, "COMPUTE_TMPRING_SIZE"}, {0x2e18, "COMPUTE_TMPRING_SIZE"},
{0xa1b5, "SPI_INTERP_CONTROL_0"}, {0xa1b5, "SPI_INTERP_CONTROL_0"},
{0xa1ba, "SPI_TMPRING_SIZE"}, {0xa1ba, "SPI_TMPRING_SIZE"},
{0xa1c4, "SPI_SHADER_Z_FORMAT"}, {0xa1c4, "SPI_SHADER_Z_FORMAT"},
{0xa1c5, "SPI_SHADER_COL_FORMAT"}, {0xa1c5, "SPI_SHADER_COL_FORMAT"},
{0xa203, "DB_SHADER_CONTROL"}, {0xa203, "DB_SHADER_CONTROL"},
{0xa08f, "CB_SHADER_MASK"}, {0xa08f, "CB_SHADER_MASK"},
{0xa1b6, "SPI_PS_IN_CONTROL"},
{0xa191, "SPI_PS_INPUT_CNTL_0"}, {0xa191, "SPI_PS_INPUT_CNTL_0"},
{0xa192, "SPI_PS_INPUT_CNTL_1"}, {0xa192, "SPI_PS_INPUT_CNTL_1"},
{0xa193, "SPI_PS_INPUT_CNTL_2"}, {0xa193, "SPI_PS_INPUT_CNTL_2"},
{0xa194, "SPI_PS_INPUT_CNTL_3"}, {0xa194, "SPI_PS_INPUT_CNTL_3"},
{0xa195, "SPI_PS_INPUT_CNTL_4"}, {0xa195, "SPI_PS_INPUT_CNTL_4"},
{0xa196, "SPI_PS_INPUT_CNTL_5"}, {0xa196, "SPI_PS_INPUT_CNTL_5"},
{0xa197, "SPI_PS_INPUT_CNTL_6"}, {0xa197, "SPI_PS_INPUT_CNTL_6"},
{0xa198, "SPI_PS_INPUT_CNTL_7"}, {0xa198, "SPI_PS_INPUT_CNTL_7"},
Show All 34 Lines const char *Name;
{0xa299, "VGT_GSVS_RING_OFFSET_2"}, {0xa299, "VGT_GSVS_RING_OFFSET_2"},
{0xa29a, "VGT_GSVS_RING_OFFSET_3"}, {0xa29a, "VGT_GSVS_RING_OFFSET_3"},
{0xa2e4, "VGT_GS_INSTANCE_CNT"}, {0xa2e4, "VGT_GS_INSTANCE_CNT"},
{0xa297, "VGT_GS_PER_VS"}, {0xa297, "VGT_GS_PER_VS"},
{0xa29b, "VGT_GS_OUT_PRIM_TYPE"}, {0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
{0xa2ac, "VGT_GSVS_RING_ITEMSIZE"}, {0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
{0xa2d5, "VGT_SHADER_STAGES_EN"},
{0xa2ad, "VGT_REUSE_OFF"}, {0xa2ad, "VGT_REUSE_OFF"},
{0xa1b8, "SPI_BARYC_CNTL"}, {0xa1b8, "SPI_BARYC_CNTL"},
{0x2c4c, "SPI_SHADER_USER_DATA_VS_0"}, {0x2c4c, "SPI_SHADER_USER_DATA_VS_0"},
{0x2c4d, "SPI_SHADER_USER_DATA_VS_1"}, {0x2c4d, "SPI_SHADER_USER_DATA_VS_1"},
{0x2c4e, "SPI_SHADER_USER_DATA_VS_2"}, {0x2c4e, "SPI_SHADER_USER_DATA_VS_2"},
{0x2c4f, "SPI_SHADER_USER_DATA_VS_3"}, {0x2c4f, "SPI_SHADER_USER_DATA_VS_3"},
{0x2c50, "SPI_SHADER_USER_DATA_VS_4"}, {0x2c50, "SPI_SHADER_USER_DATA_VS_4"},
▲ Show 20 Lines • Show All 354 Lines • Show Last 20 Lines